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| author | Tristan Gingold <tgingold@free.fr> | 2018-11-10 07:51:12 +0100 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2018-11-10 07:51:12 +0100 |
| commit | 8f35f3dc75e039479965218e7c6e1e34a4d8ff93 (patch) | |
| tree | 73ad59edff5bf6889dd0cf59f36d23c9797f812d /testsuite/gna/issue642/repro.vhdl | |
| parent | 3bd4d200a891ac813d60aa6bd9d055f43da972d6 (diff) | |
| download | ghdl-8f35f3dc75e039479965218e7c6e1e34a4d8ff93.tar.gz ghdl-8f35f3dc75e039479965218e7c6e1e34a4d8ff93.tar.bz2 ghdl-8f35f3dc75e039479965218e7c6e1e34a4d8ff93.zip | |
Add testcase for #642
Close #642
Diffstat (limited to 'testsuite/gna/issue642/repro.vhdl')
| -rw-r--r-- | testsuite/gna/issue642/repro.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/gna/issue642/repro.vhdl b/testsuite/gna/issue642/repro.vhdl new file mode 100644 index 000000000..e1288f47a --- /dev/null +++ b/testsuite/gna/issue642/repro.vhdl @@ -0,0 +1,18 @@ +entity repro is +end entity; + +architecture a of repro is + signal Combined : bit_vector(16 downto 0); + + signal SingleBit : bit; + signal Part1 : bit_vector(7 downto 0); + signal Part2 : bit_vector(7 downto 0); +begin + process + begin + (Part1, Part2) <= Combined(Combined'left - 1 downto 0); + (SingleBit, Part1, Part2) <= Combined; + wait; + end process; +end architecture; + |