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| author | Tristan Gingold <tgingold@free.fr> | 2018-09-18 18:57:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-09-18 18:57:22 +0200 |
| commit | 3fe3b89f3ea03db6f78529ded6792ec3cda42fe8 (patch) | |
| tree | 1ec62215f9655fd5563aefafdf00bd61dfaa3384 /testsuite/gna/issue648/repro.vhdl | |
| parent | 262c190bfdca756a989ca31b702700ec34d335fc (diff) | |
| download | ghdl-3fe3b89f3ea03db6f78529ded6792ec3cda42fe8.tar.gz ghdl-3fe3b89f3ea03db6f78529ded6792ec3cda42fe8.tar.bz2 ghdl-3fe3b89f3ea03db6f78529ded6792ec3cda42fe8.zip | |
Fix testcase directory name (#649 -> #648).
Diffstat (limited to 'testsuite/gna/issue648/repro.vhdl')
| -rw-r--r-- | testsuite/gna/issue648/repro.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/gna/issue648/repro.vhdl b/testsuite/gna/issue648/repro.vhdl new file mode 100644 index 000000000..fe23ad7f7 --- /dev/null +++ b/testsuite/gna/issue648/repro.vhdl @@ -0,0 +1,12 @@ +entity repro is +end entity; + +architecture h of repro is + constant L :positive := 9 + now / 1 ns; + signal s :bit_vector(31 downto 0); + alias a :bit_vector(L-1 downto 2) is s(L-1 downto 2); + signal b :bit_vector(L-1 downto 2); +begin + a <= b; +end architecture; + |