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author | Tristan Gingold <tgingold@free.fr> | 2018-10-18 06:29:48 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-10-21 08:03:37 +0200 |
commit | f910e02797a83d0c5748768d20359a3d95569cc7 (patch) | |
tree | b979d295d880af3cf10f54e9fd2708e07d5e1ec6 /testsuite/gna/issue668/tb.vhdl | |
parent | ffa1a498dc22b7758d096cd91c61f0d356879e47 (diff) | |
download | ghdl-f910e02797a83d0c5748768d20359a3d95569cc7.tar.gz ghdl-f910e02797a83d0c5748768d20359a3d95569cc7.tar.bz2 ghdl-f910e02797a83d0c5748768d20359a3d95569cc7.zip |
Add testcase for #668
Diffstat (limited to 'testsuite/gna/issue668/tb.vhdl')
-rw-r--r-- | testsuite/gna/issue668/tb.vhdl | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/testsuite/gna/issue668/tb.vhdl b/testsuite/gna/issue668/tb.vhdl new file mode 100644 index 000000000..768038201 --- /dev/null +++ b/testsuite/gna/issue668/tb.vhdl @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; + +package wishbone_pkg is +--./wb_demux_tb:internal error: wave.create_type + type t_wishbone_master_out is record + dat : std_logic_vector; + end record; + subtype t_wishbone_slave_in is t_wishbone_master_out; +end wishbone_pkg; + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +library work; +use work.wishbone_pkg.all; + +entity wb_demux is + Port ( + wbs_i : in t_wishbone_slave_in + ); +end wb_demux; +architecture full_regs of wb_demux is +begin +end full_regs; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.wishbone_pkg.all; + +entity wb_demux_tb is +end entity; +architecture bench of wb_demux_tb is + signal wbs_i : t_wishbone_slave_in( + dat(32-1 downto 0) + ); +begin + stimulus : process + begin + wbs_i.dat <= x"deadbeef"; + wait for 100 ns; + report "pass" severity note; + wait; + end process; + + dut : entity work.wb_demux + port map ( + wbs_i => wbs_i + ); +end architecture; + |