diff options
author | Tristan Gingold <tgingold@free.fr> | 2018-12-03 04:13:19 +0100 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2018-12-03 04:13:19 +0100 |
commit | 5bf6c7e02843956e2747589c78d96b9defeab32b (patch) | |
tree | ab5455e216faa971497994f3d861d43e7cbb7329 /testsuite/gna/issue676/inc2.vhdl | |
parent | 27dde16b6a7e5ba415af918dc1591880bd2e6040 (diff) | |
download | ghdl-5bf6c7e02843956e2747589c78d96b9defeab32b.tar.gz ghdl-5bf6c7e02843956e2747589c78d96b9defeab32b.tar.bz2 ghdl-5bf6c7e02843956e2747589c78d96b9defeab32b.zip |
Add testcase for #676
Diffstat (limited to 'testsuite/gna/issue676/inc2.vhdl')
-rw-r--r-- | testsuite/gna/issue676/inc2.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/gna/issue676/inc2.vhdl b/testsuite/gna/issue676/inc2.vhdl new file mode 100644 index 000000000..62b301166 --- /dev/null +++ b/testsuite/gna/issue676/inc2.vhdl @@ -0,0 +1,21 @@ +library ieee ; +use ieee.std_logic_1164.all; +use ieee.numeric_std_unsigned.all; + +entity Inc2 is + +generic( + N : positive := 4 + ); + +port( + A : in std_logic_vector(N-1 downto 0); + Sum : out std_logic_vector(N downto 0) + ); + +end Inc2; + +architecture RTL of Inc2 is +begin + sum <= ('0', A) + 1; +end RTL; |