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authorTristan Gingold <tgingold@free.fr>2018-11-10 16:11:47 +0100
committerTristan Gingold <tgingold@free.fr>2018-11-10 16:11:47 +0100
commit56e74b28fe2df92739000347ce013a627dbd7ccd (patch)
tree80262953c46cb1416fa62ed22f32214c0f206e4e /testsuite/gna/issue691/tb.vhdl
parentf2da5e23513a67e282a60ac5df689eb9dbe65938 (diff)
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Add testcase for #691
Diffstat (limited to 'testsuite/gna/issue691/tb.vhdl')
-rw-r--r--testsuite/gna/issue691/tb.vhdl12
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/gna/issue691/tb.vhdl b/testsuite/gna/issue691/tb.vhdl
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+library ieee, std;
+use ieee.std_logic_1164.all;
+
+entity e1 is port(number: in std_logic_vector(15 downto 0)); end e1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb is end entity;
+architecture arch of tb is begin
+ DS: entity work.e1 port map (number => std_logic_vector(1, 15));
+end arch;