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| author | umarcor <unai.martinezcorral@ehu.eus> | 2020-08-27 09:59:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-09-16 07:57:25 +0200 |
| commit | 63fd2ca7ce387c914668f8393962751a55ac4138 (patch) | |
| tree | d1c3314e812ddb1c6b744f2708d5797db0e2103e /testsuite/python/units01/demo.vhdl | |
| parent | bec6b6245851c955fc7e16835af81a4417133e05 (diff) | |
| download | ghdl-63fd2ca7ce387c914668f8393962751a55ac4138.tar.gz ghdl-63fd2ca7ce387c914668f8393962751a55ac4138.tar.bz2 ghdl-63fd2ca7ce387c914668f8393962751a55ac4138.zip | |
py: add 'show_ports.py' to testsuite/python/units01
Diffstat (limited to 'testsuite/python/units01/demo.vhdl')
| -rw-r--r-- | testsuite/python/units01/demo.vhdl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/testsuite/python/units01/demo.vhdl b/testsuite/python/units01/demo.vhdl index 4e40f7e94..ed98c936a 100644 --- a/testsuite/python/units01/demo.vhdl +++ b/testsuite/python/units01/demo.vhdl @@ -1,4 +1,9 @@ entity e1 is +port ( + CLK: in std_logic; + RST: in std_logic; + Q: out std_logic_vector(7 downto 0) +); end e1; architecture behav of e1 is |