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Diffstat (limited to 'testsuite/python/units01/demo.vhdl')
| -rw-r--r-- | testsuite/python/units01/demo.vhdl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/testsuite/python/units01/demo.vhdl b/testsuite/python/units01/demo.vhdl index 4e40f7e94..ed98c936a 100644 --- a/testsuite/python/units01/demo.vhdl +++ b/testsuite/python/units01/demo.vhdl @@ -1,4 +1,9 @@ entity e1 is +port ( + CLK: in std_logic; + RST: in std_logic; + Q: out std_logic_vector(7 downto 0) +); end e1; architecture behav of e1 is |