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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-17 13:11:32 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2021-06-17 21:34:16 +0200 |
| commit | 4ec5cdcd77aa1b6fc384197e1208061d62f16ba2 (patch) | |
| tree | 3c386d35b39b001db4e128abda379ddeb5ba7b2c /testsuite/pyunit/SimpleEntity.vhdl | |
| parent | 1eea725dedae1fe3eee47c2b4bfc18c7ac35e806 (diff) | |
| download | ghdl-4ec5cdcd77aa1b6fc384197e1208061d62f16ba2.tar.gz ghdl-4ec5cdcd77aa1b6fc384197e1208061d62f16ba2.tar.bz2 ghdl-4ec5cdcd77aa1b6fc384197e1208061d62f16ba2.zip | |
Updates to the dom namespace in pyGHDL.
Diffstat (limited to 'testsuite/pyunit/SimpleEntity.vhdl')
| -rw-r--r-- | testsuite/pyunit/SimpleEntity.vhdl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl index a61c1cf93..98d0afbb7 100644 --- a/testsuite/pyunit/SimpleEntity.vhdl +++ b/testsuite/pyunit/SimpleEntity.vhdl @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity e1 is +entity entity_1 is generic ( BITS : positive := 8 ); @@ -11,9 +11,9 @@ entity e1 is Reset: in std_logic; Q: out std_logic_vector(BITS - 1 downto 0) ); -end entity e1; +end entity entity_1; -architecture behav of e1 is +architecture behav of entity_1 is begin process(Clock) begin |