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authorPatrick Lehmann <Patrick.Lehmann@plc2.de>2022-12-05 21:39:51 +0100
committertgingold <tgingold@users.noreply.github.com>2022-12-06 07:23:44 +0100
commit9824b3c9a8d2103a5ecd77ff957536fa16c24bbf (patch)
tree5e870dfeaed5db9899a20bb5e10b963333bcc487 /testsuite/pyunit/libghdl/DesignComment.vhdl
parent60c43acaf82696dabdbf8a88138a656a9bde982c (diff)
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Reorganized testcases.
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-rw-r--r--testsuite/pyunit/libghdl/DesignComment.vhdl14
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diff --git a/testsuite/pyunit/libghdl/DesignComment.vhdl b/testsuite/pyunit/libghdl/DesignComment.vhdl
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--- a/testsuite/pyunit/libghdl/DesignComment.vhdl
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@@ -1,14 +0,0 @@
--- No copyright for :accum: design.
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity accum is
- port (
- -- :a: and :b: are the inputs of the adder.
- a, b : in std_logic_vector (31 downto 0);
- -- :res: is the result of the adder.
- res : out std_logic_vector (31 downto 0)
- );
-end accum;
-