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author | Tristan Gingold <tgingold@free.fr> | 2019-07-20 11:03:24 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-20 11:03:24 +0200 |
commit | a4dc62f6b5a8886085cf9364a66f3a118ff020e3 (patch) | |
tree | 8ab3c49e0cca15869df9f192f186d9f28b5c5448 /testsuite/synth/func01/func01.vhdl | |
parent | 7f2f55567c971b2478e84657ba701856109c56a9 (diff) | |
download | ghdl-a4dc62f6b5a8886085cf9364a66f3a118ff020e3.tar.gz ghdl-a4dc62f6b5a8886085cf9364a66f3a118ff020e3.tar.bz2 ghdl-a4dc62f6b5a8886085cf9364a66f3a118ff020e3.zip |
synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/func01/func01.vhdl')
-rw-r--r-- | testsuite/synth/func01/func01.vhdl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/func01/func01.vhdl b/testsuite/synth/func01/func01.vhdl new file mode 100644 index 000000000..67d203907 --- /dev/null +++ b/testsuite/synth/func01/func01.vhdl @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity func01 is + generic (l : natural := 3); + port (a : std_logic_vector (7 downto 0); + sel : std_logic; + b : out std_logic_vector (7 downto 0)); +end func01; + +architecture behav of func01 is + function gen_mask (len : natural) return std_logic_vector is + variable res : std_logic_vector (7 downto 0); + begin + res := (others => '0'); + res (len downto 0) := (others => '1'); + return res; + end gen_mask; + +begin + process (a, sel) + begin + if sel = '1' then + b <= a and gen_mask (l); + else + b <= a; + end if; + end process; +end behav; + |