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author | Tristan Gingold <tgingold@free.fr> | 2019-07-20 11:03:24 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-20 11:03:24 +0200 |
commit | a4dc62f6b5a8886085cf9364a66f3a118ff020e3 (patch) | |
tree | 8ab3c49e0cca15869df9f192f186d9f28b5c5448 /testsuite/synth/func01/func02.vhdl | |
parent | 7f2f55567c971b2478e84657ba701856109c56a9 (diff) | |
download | ghdl-a4dc62f6b5a8886085cf9364a66f3a118ff020e3.tar.gz ghdl-a4dc62f6b5a8886085cf9364a66f3a118ff020e3.tar.bz2 ghdl-a4dc62f6b5a8886085cf9364a66f3a118ff020e3.zip |
synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/func01/func02.vhdl')
-rw-r--r-- | testsuite/synth/func01/func02.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/func01/func02.vhdl b/testsuite/synth/func01/func02.vhdl new file mode 100644 index 000000000..9476c9130 --- /dev/null +++ b/testsuite/synth/func01/func02.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity func02 is + port (a : std_logic_vector (7 downto 0); + b : out std_logic_vector (7 downto 0)); +end func02; + +architecture behav of func02 is + function gen_mask (len : natural) return std_logic_vector is + variable res : std_logic_vector (len - 1 downto 0); + begin + res := (0 => '1', others => '0'); + return res; + end gen_mask; + +begin + b <= a and gen_mask (8); +end behav; + |