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authorTristan Gingold <tgingold@free.fr>2019-07-20 11:03:24 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-20 11:03:24 +0200
commita4dc62f6b5a8886085cf9364a66f3a118ff020e3 (patch)
tree8ab3c49e0cca15869df9f192f186d9f28b5c5448 /testsuite/synth/func01/tb_func03.vhdl
parent7f2f55567c971b2478e84657ba701856109c56a9 (diff)
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synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/func01/tb_func03.vhdl')
-rw-r--r--testsuite/synth/func01/tb_func03.vhdl25
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/func01/tb_func03.vhdl b/testsuite/synth/func01/tb_func03.vhdl
new file mode 100644
index 000000000..d9ef0c0eb
--- /dev/null
+++ b/testsuite/synth/func01/tb_func03.vhdl
@@ -0,0 +1,25 @@
+entity tb_func03 is
+end tb_func03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func03 is
+ signal a, b : std_logic_vector(7 downto 0);
+begin
+ dut: entity work.func03
+ port map (a, b);
+
+ process
+ begin
+ a <= x"ff";
+ wait for 1 ns;
+ assert b = x"01" severity failure;
+
+ a <= x"ee";
+ wait for 1 ns;
+ assert b = x"00" severity failure;
+
+ wait;
+ end process;
+end behav;