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authorTristan Gingold <tgingold@free.fr>2020-06-12 07:51:01 +0200
committerTristan Gingold <tgingold@free.fr>2020-06-12 07:51:01 +0200
commitd8b893bece3dfa2e421a7d92399fa913839c9220 (patch)
treea656ee768566572594d16258a95d1ddec8ea37ac /testsuite/synth/issue1366/issue.vhdl
parentdb9c1fd3700995155b2d8a32d929b3d0dc9689e2 (diff)
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testsuite/synth: add test for #1366
Diffstat (limited to 'testsuite/synth/issue1366/issue.vhdl')
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diff --git a/testsuite/synth/issue1366/issue.vhdl b/testsuite/synth/issue1366/issue.vhdl
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+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+
+entity sequencer is
+ generic (
+ seq : string
+ );
+ port (
+ clk : in std_logic;
+ data : out std_logic
+ );
+end entity sequencer;
+
+
+architecture rtl of sequencer is
+
+ signal index : natural := seq'low;
+
+ function to_bit (a : in character) return std_logic is
+ variable ret : std_logic;
+ begin
+ case a is
+ when '0' | '_' => ret := '0';
+ when '1' | '-' => ret := '1';
+ when others => ret := 'X';
+ end case;
+ return ret;
+ end function to_bit;
+
+begin
+
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if (index < seq'high) then
+ index <= index + 1;
+ end if;
+ end if;
+ end process;
+
+ data <= to_bit(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+
+entity issue is
+ port (
+ clk : in std_logic
+ );
+end entity issue;
+
+
+architecture psl of issue is
+
+ component sequencer is
+ generic (
+ seq : string
+ );
+ port (
+ clk : in std_logic;
+ data : out std_logic
+ );
+ end component sequencer;
+
+ signal a, b : std_logic;
+
+begin
+
+
+ -- 0123456789
+ SEQ_A : sequencer generic map ("__-__-____") port map (clk, a);
+ SEQ_B : sequencer generic map ("__-__-____") port map (clk, b);
+
+
+end architecture psl;