testsuite/synth: add a test for #2369

1 files changed, 15 insertions, 0 deletions

diff --git a/testsuite/synth/issue2369/bug.vhdl b/testsuite/synth/issue2369/bug.vhdl
new file mode 100644
index 000000000..df3e29787
--- /dev/null
+++ b/testsuite/synth/issue2369/bug.vhdl
@@ -0,0 +1,15 @@
+entity bug is
+  port (clk, x, y : in bit; z : out bit);
+end entity bug;
+
+architecture RTL of bug is
+begin
+
+process (clk)
+begin
+  if rising_edge(clk) then
+    z <= x when y else unaffected;
+  end if;
+end process;
+
+end architecture RTL;