synth: add testcase from issue8

1 files changed, 16 insertions, 0 deletions

diff --git a/testsuite/synth/issue8/vector8_test1.vhdl b/testsuite/synth/issue8/vector8_test1.vhdl
new file mode 100644
index 000000000..585d003b0
--- /dev/null
+++ b/testsuite/synth/issue8/vector8_test1.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector8_test1 is
+  port (led7: out std_logic);
+end vector8_test1;
+
+architecture synth of vector8_test1 is
+
+signal v : std_logic_vector(7 downto 0);
+
+begin
+  v(7) <= '1';
+  led7 <= v(7);
+end synth;