Import vests testsuite

36 files changed, 2179 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd
new file mode 100644
index 000000000..5715c84ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity SR_flipflop is
+  port ( S, R : in bit;  Q : out bit );
+end entity SR_flipflop;
+
+--------------------------------------------------
+
+architecture checking of SR_flipflop is
+begin
+
+    set_reset : process (S, R) is
+    begin
+      assert S = '1' nand R = '1';
+      if S = '1' then
+        Q <= '1';
+      end if;
+      if R = '1' then
+        Q <= '0';
+      end if;
+    end process set_reset;
+
+end architecture checking;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd
new file mode 100644
index 000000000..508f6835d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity cos is
+  port ( theta : in real;  result : out real );
+end entity cos;
+
+--------------------------------------------------
+
+architecture series of cos is
+begin
+
+  summation : process (theta) is
+    variable sum, term : real;
+    variable n : natural;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    n := 0;
+    while abs term > abs (sum / 1.0E6) loop
+      n := n + 2;
+      term := (-term) * theta**2 / real(((n-1) * n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture series;
+
+
+architecture fixed_length_series of cos is
+begin
+
+  summation : process (theta) is
+    variable sum, term : real;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    for n in 1 to 9 loop
+      term := (-term) * theta**2 / real(((2*n-1) * 2*n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture fixed_length_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
new file mode 100644
index 000000000..359a22ead
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity counter is
+  port ( clk, reset : in bit;  count : out natural );
+end entity counter;
+
+--------------------------------------------------
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+    variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      loop
+        wait until clk = '1' or reset = '1';
+        exit when reset = '1';
+        count_value := (count_value + 1) mod 16;
+        count <= count_value;
+      end loop;
+      -- at this point, reset = '1'
+      count_value := 0;
+      count <= count_value;
+      wait until reset = '0';
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd
new file mode 100644
index 000000000..37c586cfc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity counter is
+  port ( clk : in bit;  count : out natural );
+end entity counter;
+
+--------------------------------------------------
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+    variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      wait until clk = '1';
+      count_value := (count_value + 1) mod 16;
+      count <= count_value;
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
new file mode 100644
index 000000000..b8bdf9b76
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity edge_triggered_register is
+  port ( clock : in bit; 
+         d_in : in real;  d_out : out real );
+end entity edge_triggered_register;
+
+--------------------------------------------------
+
+architecture check_timing of edge_triggered_register is
+begin
+
+  store_and_check : process (clock) is
+    variable stored_value : real;
+    variable pulse_start : time;
+  begin
+    case clock is
+      when '1' =>
+        pulse_start := now;
+        stored_value := d_in;
+        d_out <= stored_value;
+      when '0' =>
+        assert now = 0 ns or (now - pulse_start) >= 5 ns
+          report "clock pulse too short"; 
+    end case;
+  end process store_and_check;
+
+end architecture check_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt
new file mode 100644
index 000000000..25a2efcee
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt
@@ -0,0 +1,47 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                        Chapter 3 - Sequential Statements
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure
+-----------                                     ------------                            --------------                  -------
+thermostat-1.vhd                                entity thermostat                       example                         Figure 3-1
+mux4.vhd                                        package mux4_types                      body                            Section 3.2
+--                                              entity mux4                             demo                            Figure 3-2
+counter.vhd                                     entity counter                          behavior                        Figure 3-3
+counter-1.vhd                                   entity counter                          behavior                        Figure 3-4
+cos.vhd                                         entity cos                              series                          Figure 3-5
+--                                                                                      fixed_length_series             Figure 3-6
+SR_flipflop.vhd                                 entity SR_flipflop                      checking                        Figure 3-7
+max3.vhd                                        entity max3                             check_error                     Figure 3-8
+edge_triggered_register.vhd                     entity edge_triggered_register          check_timing                    Figure 3-9
+inline_01.vhd                                   entity inline_01                        test                            Section 3.1
+inline_02.vhd                                   entity inline_02                        test                            Section 3.1
+inline_03.vhd                                   entity inline_03                        test                            Section 3.1
+inline_04a.vhd                                  entity inline_04a                       test                            Section 3.1
+inline_05.vhd                                   entity inline_05                        test                            Section 3.1
+inline_06.vhd                                   entity inline_06                        test                            Section 3.2
+inline_07.vhd                                   entity inline_07                        test                            Section 3.2
+inline_08.vhd                                   entity inline_08                        test                            Section 3.2
+inline_09.vhd                                   entity inline_09                        test                            Section 3.2
+inline_10a.vhd                                  entity inline_10a                       test                            Section 3.3
+inline_11.vhd                                   entity inline_11                        test                            Section 3.3
+inline_12.vhd                                   entity inline_12                        test                            Section 3.4
+inline_13.vhd                                   entity inline_13                        test                            Section 3.4
+inline_14.vhd                                   entity inline_14                        test                            Section 3.4
+inline_15.vhd                                   entity inline_15                        test                            Section 3.4
+inline_16.vhd                                   entity inline_16                        test                            Section 3.4
+inline_17.vhd                                   entity inline_17                        test                            Section 3.4
+inline_18.vhd                                   entity inline_18                        test                            Section 3.5
+inline_19.vhd                                   entity inline_19                        test                            Section 3.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_mux4.vhd                                     entity tb_mux4                          test_demo                       mux4.vhd
+tb_counter.vhd                                  entity tb_counter                       test_behavior                   counter.vhd
+tb_counter-1.vhd                                entity tb_counter                       test_behavior                   counter-1.vhd
+tb_cos.vhd                                      entity tb_cos                           test_series                     cos.vhd
+tb_cos-1.vhd                                    entity tb_cos                           test_fixed_length_series        cos.vhd
+tb_SR_flipflop.vhd                              tb_SR_flipflop                          test_checking                   SR_flipflop.vhd
+tb_max3.vhd                                     entity tb_max3                          test_check_error                max3.vhd
+tb_edge_triggered_register.vhd                  entity tb_edge_triggered_register       test_check_timing               edge_triggered_register.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd
new file mode 100644
index 000000000..022459e6d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+  signal en : bit := '0';
+  signal data_in : integer := 0;
+
+begin
+
+  process_1_a : process (en, data_in) is
+
+    variable stored_value : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    if en = '1' then
+      stored_value := data_in;
+    end if;
+
+    -- end of code from book
+
+  end process process_1_a;
+
+  stimulus : process is
+  begin
+    en <= '1' after 10 ns, '0' after 20 ns;
+    data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
new file mode 100644
index 000000000..fa2e3249e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+  signal sel : integer range 0 to 1 := 0;
+  signal input_0 : integer := 0;
+  signal input_1 : integer := 10;
+  signal result : integer;
+
+begin
+
+  process_1_b : process (sel, input_0, input_1) is
+  begin
+
+    -- code from book:
+
+    if sel = 0 then
+      result <= input_0;  -- executed if sel = 0
+    else
+      result <= input_1;  -- executed if sel /= 0
+    end if;
+
+    -- end of code from book
+
+  end process process_1_b;
+
+  stimulus : process is
+  begin
+    sel <= 1 after 40 ns;
+    input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
+    input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd
new file mode 100644
index 000000000..f997c913b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+  process_1_c : process is
+
+    type mode_type is (immediate, other_mode);
+    type opcode_type is (load, add, subtract, other_opcode);
+
+    variable mode : mode_type;
+    variable opcode : opcode_type;
+    constant immed_operand : integer := 1;
+    constant memory_operand : integer := 2;
+    constant address_operand : integer := 3;
+    variable operand : integer;
+
+    procedure procedure_1_c is
+    begin
+
+      -- code from book:
+
+      if mode = immediate then
+        operand := immed_operand;
+      elsif opcode = load or opcode = add or opcode = subtract then
+        operand := memory_operand;
+      else
+        operand := address_operand;
+      end if;
+
+      -- end of code from book
+
+    end procedure_1_c;
+
+  begin
+    mode := immediate;
+    procedure_1_c;
+
+    mode := other_mode;
+    opcode := load;
+    procedure_1_c;
+
+    opcode := add;
+    procedure_1_c;
+
+    opcode := subtract;
+    procedure_1_c;
+
+    opcode := other_opcode;
+    procedure_1_c;
+
+    wait;
+  end process process_1_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
new file mode 100644
index 000000000..ae1c5af6b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+
+  type gear_type is (gear_1, gear_2, neutral);
+  signal gear : gear_type := gear_1;
+
+  signal gear_engaged : boolean := false;
+
+begin
+
+  process_1_d : process (gear) is
+
+    variable max_acceleration : real := 0.0;
+    variable reverse_indicator : boolean := true;
+
+  begin
+
+    -- code from book:
+
+    if gear = neutral then
+      max_acceleration := 0.0;
+      reverse_indicator := false;
+      gear_engaged <= false;
+    end if;
+
+    -- end of code from book
+
+  end process process_1_d;
+
+  stimulus : process is
+  begin
+    gear <= gear_2 after 100 ns, neutral after 200 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd
new file mode 100644
index 000000000..30c27654a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  type phase_type is (wash, other_phase);
+  signal phase : phase_type := other_phase;
+
+  type cycle_type is (delicate_cycle, other_cycle);
+  signal cycle_select : cycle_type := delicate_cycle;
+
+  type speed_type is (slow, fast);
+  signal agitator_speed : speed_type := slow;
+
+  signal agitator_on : boolean := false;
+
+begin
+
+  process_1_e : process (phase, cycle_select) is
+  begin
+
+    -- code from book:
+
+    if phase = wash then
+      if cycle_select = delicate_cycle then
+        agitator_speed <= slow;
+      else
+        agitator_speed <= fast;
+      end if;
+      agitator_on <= true;
+    end if;
+
+    -- end of code from book
+
+  end process process_1_e;
+
+  stimulus : process is
+  begin
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= wash;			wait for 100 ns;
+    cycle_select <= delicate_cycle;	wait for 100 ns;
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= other_phase;		wait for 100 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd
new file mode 100644
index 000000000..5fb91e479
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  -- code from book:
+  
+  type alu_func is (pass1, pass2, add, subtract);
+  
+  -- end of code from book
+  
+  signal func : alu_func := pass1;
+  signal operand1 : integer := 10;
+  signal operand2 : integer := 3;
+
+begin
+
+  process_2_a : process (func, operand1, operand2) is
+
+    variable result : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    case func is
+      when pass1 =>
+        result := operand1;
+      when pass2 =>
+        result := operand2;
+      when add =>
+        result := operand1 + operand2;
+      when subtract =>
+        result := operand1 - operand2;
+    end case;
+
+    -- end of code from book
+
+  end process process_2_a;
+
+
+  stimulus : process is
+  begin
+    func <= pass2 after 10 ns,
+	    add after 20 ns,
+	    subtract after 30 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
new file mode 100644
index 000000000..461363079
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+begin
+
+  process_2_b : process is
+
+    -- code from book:
+
+    subtype index_mode is integer range 0 to 3;
+
+    variable instruction_register : integer range 0 to 2**16 - 1;
+
+    -- end of code from book
+
+    variable index_value : integer;
+    constant accumulator_A : integer := 1;
+    constant accumulator_B : integer := 2;
+    constant index_register : integer := 3;
+
+  begin
+
+    for i in index_mode loop
+      instruction_register := i * 2**12;
+
+      -- code from book:
+
+      case index_mode'((instruction_register / 2**12) rem 2**2) is
+        when 0 =>
+          index_value := 0;
+        when 1 =>
+          index_value := accumulator_A;
+        when 2 =>
+          index_value := accumulator_B;
+        when 3 =>
+          index_value := index_register;
+      end case;
+
+      -- end of code from book
+
+    end loop;
+
+    wait;
+  end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd
new file mode 100644
index 000000000..7c5496ad7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+  process_2_c : process is
+
+    -- code from book:
+
+    type opcodes is
+      (nop, add, subtract, load, store, jump, jumpsub, branch, halt);
+
+    subtype control_transfer_opcodes is opcodes range jump to branch;
+
+    -- end of code from book
+
+    variable opcode : opcodes;
+    variable operand : integer;
+    constant memory_operand : integer := 1;
+    constant address_operand : integer := 2;
+
+  begin
+
+    for i in opcodes loop
+      opcode := i;
+
+      -- code from book:
+
+      case opcode is
+        when load | add | subtract =>
+          operand := memory_operand;
+        when store | jump | jumpsub | branch =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      --
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+        when branch downto store =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      -- end of code from book
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+        -- code from book:
+        when control_transfer_opcodes | store =>
+          operand := address_operand;
+        -- end of code from book
+        when others =>
+          operand := 0;
+      end case;
+
+    end loop;
+
+    wait;
+  end process process_2_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
new file mode 100644
index 000000000..9539cca2c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+
+  process_2_d : process is
+
+    -- code from book:
+
+    variable N : integer := 1;
+
+    --
+
+    constant C : integer := 1;
+
+    -- end of code from book
+
+    constant expression : integer := 7;
+
+  begin
+
+    -- code from book:
+
+    -- error: Case choice must be a locally static expression
+
+    -- case expression is         -- example of an illegal case statement
+    --   when N | N+1 => -- . . .
+    --   when N+2 to N+5 => -- . . .
+    --   when others => -- . . .
+    -- end case;
+
+    --
+
+    case expression is
+      when C | C+1 => -- . . .
+      when C+2 to C+5 => -- . . .
+      when others => -- . . .
+    end case;
+
+    -- end of code from book
+
+    wait;
+  end process process_2_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
new file mode 100644
index 000000000..8911f431f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_10a is
+
+end entity inline_10a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10a is
+
+  -- code from book:
+
+  type stick_position is (down, center, up);
+
+  -- end of code from book
+
+  signal throttle : stick_position;
+
+begin
+
+
+  process_3_a : process (throttle) is
+
+    variable speed : integer := 0;
+    constant decrement : integer := 1;
+    constant increment : integer := 1;
+
+  begin
+
+    -- code from book:
+
+    case throttle is
+      when down =>
+        speed := speed - decrement;
+      when up =>
+        speed := speed + increment;
+      when center =>
+        null; -- no change to speed
+    end case;
+
+    -- end of code from book
+
+  end process process_3_a;
+
+
+  stimulus : process is
+  begin
+    throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd
new file mode 100644
index 000000000..a03dfa75d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+  signal sensitivity_list : bit := '0';
+
+begin
+
+
+  -- code from book:
+
+  -- make "sensitivity_list" roman italic
+  control_section : process ( sensitivity_list ) is
+  begin
+    null;
+  end process control_section;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
new file mode 100644
index 000000000..c6170470c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+begin
+
+
+  process_4_a : process is
+
+    constant condition, condition_1,
+             condition_2, condition_3 : boolean := true;
+    variable index : integer;
+
+  begin
+
+    -- code from book: syntax check only
+
+    -- change "condition" to roman italic
+
+    -- not in book:
+    loop
+    -- end not in book
+
+    if condition then
+      exit;
+    end if;
+
+    -- not in book:
+    end loop;
+    -- end not in book
+
+    --
+
+    -- change "condition" to roman italic
+
+    loop
+      -- . . .
+      exit when condition;
+      -- . . .
+    end loop;
+    -- . . .      -- control transferred to here
+                  -- when condition becomes true within the loop
+
+    --
+
+    loop_name : loop
+      -- . . .
+      exit loop_name;
+      -- . . .
+    end loop loop_name ;
+
+    --
+
+    -- change conditions to roman italic with hyphens
+
+    outer : loop
+      -- . . .
+      inner : loop
+         -- . . .
+        exit outer when condition_1; -- exit 1
+        -- . . .
+        exit when condition_2;       -- exit 2
+        -- . . .
+      end loop inner;
+      -- . . .                      -- target A
+      exit outer when condition_3;   -- exit 3
+       -- . . .
+    end loop outer;
+    -- . . .                        -- target B
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      next when condition;
+      -- statement_2;
+    end loop;
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      if not condition then
+        -- statement_2;
+      end if;
+    end loop;
+
+    --
+
+    while index > 0 loop
+      -- . . .      -- statement A: do something with index
+    end loop;
+    -- . . .    -- statement B
+
+
+    -- end of code from book
+
+    wait;
+  end process process_4_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd
new file mode 100644
index 000000000..b2ab59683
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_13 is
+
+  signal count_out : integer;
+
+begin
+
+
+  process_4_b : process is
+  begin
+
+    -- code from book:
+
+    for count_value in 0 to 127 loop
+      count_out <= count_value;
+      wait for 5 ns;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_b;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd
new file mode 100644
index 000000000..09ee78785
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_14 is
+
+end entity inline_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14 is
+
+    -- code from book:
+
+    type controller_state is (initial, idle, active, error);
+
+    -- end of code from book
+
+  signal current_state : controller_state := initial;
+
+begin
+
+
+  process_4_c : process is
+  begin
+
+    -- code from book:
+
+    for state in controller_state loop
+      -- . . .
+      -- not in book:
+      current_state <= state;
+      wait for 10 ns;
+      -- end not in book
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_c;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd
new file mode 100644
index 000000000..70860667c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_15 is
+
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+begin
+
+  -- code from book:
+
+  erroneous : process is
+    variable i, j : integer;
+  begin
+    i := loop_param;          -- error!
+    for loop_param in 1 to 10 loop
+      loop_param := 5;        -- error!
+    end loop;
+    j := loop_param;          -- error!
+  end process erroneous;
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd
new file mode 100644
index 000000000..f75a6ce62
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+begin
+
+  -- code from book:
+
+  hiding_example : process is
+    variable a, b : integer;
+  begin
+    a := 10;
+    for a in 0 to 7 loop
+      b := a;
+    end loop;
+    -- a = 10, and b = 7
+    -- . . .
+    -- not in book:
+    wait;
+    -- end not in book
+  end process hiding_example;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
new file mode 100644
index 000000000..f4983840e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_17 is
+
+end entity inline_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_17 is
+begin
+
+
+  process_4_f : process is
+  begin
+
+    -- code from book:
+
+    for i in 10 to 1 loop
+      -- . . .
+    end loop;
+
+    for i in 10 downto 1 loop
+      -- . . .
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_f;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd
new file mode 100644
index 000000000..87917a50e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_18 is
+
+end entity inline_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_18 is
+begin
+
+
+  process_5_a : process is
+
+    constant initial_value : natural := 10;
+    constant max_value : natural := 8;
+    constant current_character : character := 'A';
+    constant input_string : string := "012ABC";
+    constant free_memory : natural := 0;
+    constant low_water_limit : natural := 1024;
+    constant packet_length : natural := 0;
+    constant clock_pulse_width : delay_length := 10 ns;
+    constant min_clock_width : delay_length := 20 ns;
+    constant last_position : natural := 10;
+    constant first_position : natural := 5;
+    constant number_of_entries : natural := 0;
+
+  begin
+
+    -- code from book:
+
+    assert initial_value <= max_value;
+
+    --
+
+    assert initial_value <= max_value
+      report "initial value too large";
+
+    --
+
+    assert current_character >= '0' and current_character <= '9'
+      report "Input number " & input_string & " contains a non-digit";
+
+    --
+
+    assert free_memory >= low_water_limit
+      report "low on memory, about to start garbage collect"
+      severity note;
+
+    --
+
+    assert packet_length /= 0
+      report "empty network packet received"
+      severity warning;
+
+    --
+
+    assert clock_pulse_width >= min_clock_width
+      severity error;
+
+    --
+
+    assert (last_position - first_position + 1) = number_of_entries
+      report "inconsistency in buffer model"
+      severity failure;
+
+    -- end of code from book
+
+    wait;
+  end process process_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd
new file mode 100644
index 000000000..6a3c9592f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_19 is
+
+end entity inline_19;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_19 is
+
+  subtype data_type is integer;
+
+  signal transmit_data : data_type := 0;
+
+begin
+
+
+  -- code from book:
+  
+  transmit_element : process (transmit_data) is
+    -- . . .      -- variable declarations
+  begin
+    report "transmit_element: data = "
+        & data_type'image(transmit_data);
+    -- . . .
+  end process transmit_element;
+
+  -- end of code from book
+
+
+  stimulus : process is
+  begin
+    transmit_data <= 10 after 10 ns, 20 after 20 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
new file mode 100644
index 000000000..cf515d462
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity max3 is
+  port ( a, b, c : in integer;  z : out integer );
+end entity max3;
+
+--------------------------------------------------
+
+architecture check_error of max3 is
+begin
+
+    maximizer : process (a, b, c)
+      variable result : integer;
+    begin
+      if a > b then
+        if a > c then
+          result := a;
+        else
+          result := a;  -- Oops!  Should be: result := c;
+        end if;
+      elsif  b > c then
+        result := b;
+      else
+        result := c;
+      end if;
+      assert result >= a and result >= b and result >= c
+        report "inconsistent result for maximum"
+        severity failure;
+      z <= result;
+    end process maximizer;
+
+end architecture check_error;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
new file mode 100644
index 000000000..da1831913
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- test code:
+
+package mux4_types is
+
+  -- code from book:
+
+  type sel_range is range 0 to 3;
+
+  -- end of code from book
+
+end package mux4_types;
+
+
+
+use work.mux4_types.all;
+
+-- end test code
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity mux4 is
+  port ( sel : in sel_range;
+         d0, d1, d2, d3 : in std_ulogic;
+         z : out std_ulogic );
+end entity mux4;
+
+--------------------------------------------------
+
+architecture demo of mux4 is
+begin
+
+  out_select : process (sel, d0, d1, d2, d3) is
+  begin
+    case sel is
+      when 0 => 
+        z <= d0;
+      when 1 => 
+        z <= d1;
+      when 2 => 
+        z <= d2;
+      when 3 => 
+        z <= d3;
+    end case;
+  end process out_select;
+
+end architecture demo;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd
new file mode 100644
index 000000000..dc67dcd56
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_SR_flipflop is
+
+end entity tb_SR_flipflop;
+
+
+----------------------------------------------------------------
+
+
+architecture test_checking of tb_SR_flipflop is
+
+  signal S, R, Q : bit := '0';
+
+begin
+
+  dut : entity work.SR_flipflop(checking)
+    port map ( S => S, R => R, Q => Q );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '1';	R <= '1';	wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_checking;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd
new file mode 100644
index 000000000..45799a0ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_cos is
+
+end entity tb_cos;
+
+
+----------------------------------------------------------------
+
+
+architecture test_fixed_length_series of tb_cos is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(fixed_length_series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+    constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_fixed_length_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd
new file mode 100644
index 000000000..ab0afeabc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_cos is
+
+end entity tb_cos;
+
+
+----------------------------------------------------------------
+
+
+architecture test_series of tb_cos is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+    constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
new file mode 100644
index 000000000..383732ac9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_counter is
+
+end entity tb_counter;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavior of tb_counter is
+
+  signal clk, reset : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, reset => reset, count => count );
+
+  stimulus : process is
+  begin
+
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '1' after 15 ns;
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '0' after 15 ns;
+    for cycle_count in 1 to 30 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
new file mode 100644
index 000000000..aa0dafcaa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_counter is
+
+end entity tb_counter;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavior of tb_counter is
+
+  signal clk : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, count => count );
+
+  stimulus : process is
+  begin
+    for cycle_count in 1 to 100 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd
new file mode 100644
index 000000000..bacfd0250
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_edge_triggered_register is
+
+end entity tb_edge_triggered_register;
+
+
+----------------------------------------------------------------
+
+
+architecture test_check_timing of tb_edge_triggered_register is
+
+  signal clock : bit := '0'; 
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.edge_triggered_register(check_timing)
+    port map ( clock => clock, d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 20 ns;
+
+    d_in <= 1.0;			wait for 10 ns;
+    clock <= '1', '0' after 10 ns;	wait for 20 ns;
+
+    d_in <= 2.0;			wait for 10 ns;
+    clock <= '1', '0' after 5 ns;	wait for 20 ns;
+
+    d_in <= 3.0;			wait for 10 ns;
+    clock <= '1', '0' after 4 ns;	wait for 20 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_check_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd
new file mode 100644
index 000000000..d8096eb50
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_max3 is
+
+end entity tb_max3;
+
+
+----------------------------------------------------------------
+
+
+architecture test_check_error of tb_max3 is
+
+  signal a, b, c, z : integer := 0;
+
+begin
+
+  dut : entity work.max3(check_error)
+    port map ( a => a, b => b, c => c, z => z );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    a <= 7;				wait for 10 ns;
+		b <= 10;		wait for 10 ns;
+    			    c <= 15;	wait for 10 ns;
+    a <= 12;				wait for 10 ns;
+    a <= 20;				wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_check_error;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd
new file mode 100644
index 000000000..5e76e43fd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_mux4 is
+
+end entity tb_mux4;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+
+architecture test_demo of tb_mux4 is
+
+  signal sel : work.mux4_types.sel_range := 0;
+  signal d0, d1, d2, d3, z : std_ulogic;
+
+begin
+
+  dut : entity work.mux4(demo)
+    port map ( sel => sel,
+               d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+               z => z );
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    d0 <= '1';			wait for 5 ns;
+    d1 <= 'H';			wait for 5 ns;
+    		sel <= 1;	wait for 5 ns;
+    d1 <= 'L';			wait for 5 ns;
+    		sel <= 2;	wait for 5 ns;
+    d0 <= '0';			wait for 5 ns;
+    d2 <= '1';			wait for 5 ns;
+    d2 <= '0';			wait for 5 ns;
+    		sel <= 3;	wait for 5 ns;
+    d3 <= '1';			wait for 5 ns;
+    d3 <= '0';			wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_demo;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd
new file mode 100644
index 000000000..356e7d1f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.thermal_systems.all;
+
+entity thermostat is
+  port ( quantity sensor_temp : in temperature;
+         signal desired_temp : in real;
+         signal heater_on : out boolean );
+end entity thermostat;
+
+----------------------------------------------------
+
+architecture example of thermostat is
+begin
+
+  controller : process ( desired_temp, 
+                         sensor_temp'above(desired_temp + 2.0),
+                         sensor_temp'above(desired_temp - 2.0) ) is
+  begin
+    if sensor_temp < desired_temp - 2.0 then
+      heater_on <= true;
+    elsif sensor_temp > desired_temp + 2.0 then
+      heater_on <= false;
+    end if;
+  end process controller;
+
+end architecture example;