Add testcase for #542

3 files changed, 84 insertions, 0 deletions

diff --git a/testsuite/gna/issue542/testsuite.sh b/testsuite/gna/issue542/testsuite.sh
new file mode 100755
index 000000000..b132693a1
--- /dev/null
+++ b/testsuite/gna/issue542/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=93
+analyze write.vhd
+analyze_failure wrapper.vhd
+
+clean
+
+export GHDL_STD_FLAGS=--std=08
+analyze write.vhd
+analyze_failure wrapper.vhd
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue542/wrapper.vhd b/testsuite/gna/issue542/wrapper.vhd
new file mode 100644
index 000000000..12ccd633a
--- /dev/null
+++ b/testsuite/gna/issue542/wrapper.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity wrapper is
+	port(
+	clk   : in std_logic;
+	reset : in std_logic;
+	write : in std_logic;
+	ack   : out std_logic
+);
+end wrapper;
+
+architecture a of wrapper is
+
+	-- compiling with std=93 produces an error here
+	component write is
+		port(
+					clk   : in std_logic;
+					reset : in std_logic;
+					write : in std_logic;
+					ack   : out std_logic
+				);
+	end component;
+
+begin
+
+	--dut : entity work.write(a) -- compilation works with this type of instanciation/declaration, std=08 and component declaration on line 17 commented
+	dut: component write
+		port map(
+					clk   => clk,
+					reset => reset,
+					write => write, --compiling with std=08 produces a error here
+					ack   => ack
+				);
+
+end architecture;
diff --git a/testsuite/gna/issue542/write.vhd b/testsuite/gna/issue542/write.vhd
new file mode 100644
index 000000000..d7c1fd129
--- /dev/null
+++ b/testsuite/gna/issue542/write.vhd
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity write is
+	port(
+	clk   : in std_logic;
+	reset : in std_logic;
+	write : in std_logic;
+	ack   : out std_logic
+);
+end write;
+
+architecture a of write is
+begin
+
+	process (clk, reset) is
+	begin
+		if reset = '1' then
+			ack <= '0';
+		elsif rising_edge(clk) then
+			if write = '1' then
+				ack <= '1';
+			else
+				ack <= '0';
+			end if;
+		end if;
+	end process;
+
+end architecture;