diff options
author | Tristan Gingold <tgingold@free.fr> | 2022-04-06 08:19:38 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2022-04-06 08:19:38 +0200 |
commit | 2918e833acf7f8652099cc290f465b79ad747df2 (patch) | |
tree | f51c98f3783f4fa1daa1cb3ca13865de2923756a /testsuite | |
parent | 7b3fabe10aecac99d8b4f4360c414333ee909197 (diff) | |
download | ghdl-2918e833acf7f8652099cc290f465b79ad747df2.tar.gz ghdl-2918e833acf7f8652099cc290f465b79ad747df2.tar.bz2 ghdl-2918e833acf7f8652099cc290f465b79ad747df2.zip |
testsuite/synth: add tests for #2019
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/issue2019/ent.vhdl | 26 | ||||
-rw-r--r-- | testsuite/synth/issue2019/repro1.vhdl | 28 | ||||
-rw-r--r-- | testsuite/synth/issue2019/repro2.vhdl | 13 | ||||
-rwxr-xr-x | testsuite/synth/issue2019/testsuite.sh | 10 |
4 files changed, 77 insertions, 0 deletions
diff --git a/testsuite/synth/issue2019/ent.vhdl b/testsuite/synth/issue2019/ent.vhdl new file mode 100644 index 000000000..fe4c17bf5 --- /dev/null +++ b/testsuite/synth/issue2019/ent.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port (p : out std_ulogic_vector(3 downto 0)); + type my_logic_vector is array (natural range <>) of std_ulogic; + + function to_stdlogic (value : std_ulogic) return std_ulogic is + begin + return '0'; + end function; + + function to_stdlogic (value : my_logic_vector) return std_ulogic_vector is + variable tmp : std_ulogic_vector(value'range); + begin + tmp(0) := to_stdlogic(value(0)); + --return tmp; -- uncommenting fixes it + end function; + + signal s : my_logic_vector(3 downto 0); +end entity; + +architecture a of ent is +begin + p <= to_stdlogic(s); +end architecture; diff --git a/testsuite/synth/issue2019/repro1.vhdl b/testsuite/synth/issue2019/repro1.vhdl new file mode 100644 index 000000000..fc66acb86 --- /dev/null +++ b/testsuite/synth/issue2019/repro1.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port (p : out std_ulogic_vector(3 downto 0)); +end ent; + + +architecture a of ent is + type my_logic_vector is array (natural range <>) of std_ulogic; + + function to_stdlogic (value : std_ulogic) return std_ulogic is + begin + return '0'; + end function; + + function to_stdlogic (value : my_logic_vector) return std_ulogic_vector is + variable tmp : std_ulogic_vector(value'range); + begin + tmp(0) := to_stdlogic(value(0)); + --return tmp; -- uncommenting fixes it + end function; + + signal s : my_logic_vector(3 downto 0); + +begin + p <= to_stdlogic(s); +end architecture; diff --git a/testsuite/synth/issue2019/repro2.vhdl b/testsuite/synth/issue2019/repro2.vhdl new file mode 100644 index 000000000..f2accf8fa --- /dev/null +++ b/testsuite/synth/issue2019/repro2.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro2 is + port (p : out std_ulogic_vector(3 downto 0)); + signal s : std_ulogic_vector(3 downto 0); +end entity; + +architecture a of repro2 is +begin + s <= x"3"; + p <= s; +end architecture; diff --git a/testsuite/synth/issue2019/testsuite.sh b/testsuite/synth/issue2019/testsuite.sh new file mode 100755 index 000000000..743d05083 --- /dev/null +++ b/testsuite/synth/issue2019/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only repro2 + +synth_failure repro1.vhdl -e +synth_failure ent.vhdl -e + +echo "Test successful" |