testsuite/synth: add testcase for #1609

3 files changed, 60 insertions, 0 deletions

diff --git a/testsuite/synth/issue1609/exp_psl.vhdl b/testsuite/synth/issue1609/exp_psl.vhdl
new file mode 100644
index 000000000..58558a0a0
--- /dev/null
+++ b/testsuite/synth/issue1609/exp_psl.vhdl
@@ -0,0 +1,23 @@
+library IEEE;
+  use IEEE.std_logic_1164.ALL;
+  use IEEE.numeric_std.ALL;
+
+entity exp is
+  port ( clk : in std_logic );
+end entity exp;
+
+architecture behav of exp is
+begin
+end architecture behav;
+vunit exp_formal (exp(behav))
+{
+    signal any_nat : natural;
+
+    attribute anyconst : boolean;
+    attribute anyconst of any_nat : signal is true;
+
+    default Clock is rising_edge(clk);
+
+    assume always any_nat >=10;
+    assert always any_nat >=10;
+}
diff --git a/testsuite/synth/issue1609/exp_vhd.vhdl b/testsuite/synth/issue1609/exp_vhd.vhdl
new file mode 100644
index 000000000..06a6260d7
--- /dev/null
+++ b/testsuite/synth/issue1609/exp_vhd.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+  use IEEE.std_logic_1164.ALL;
+  use IEEE.numeric_std.ALL;
+
+entity exp is
+  port (
+    clk : in    std_logic
+  );
+end entity exp;
+
+architecture behav of exp is
+
+  signal any_nat : natural;
+
+  attribute anyconst : boolean;
+  attribute anyconst of any_nat : signal is true;
+
+begin
+
+  default Clock is rising_edge(clk);
+
+  assume always any_nat >=10;
+  assert always any_nat >=10;
+
+end architecture behav;
+
diff --git a/testsuite/synth/issue1609/testsuite.sh b/testsuite/synth/issue1609/testsuite.sh
new file mode 100755
index 000000000..746e2ac52
--- /dev/null
+++ b/testsuite/synth/issue1609/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --std=08 exp_psl.vhdl -e > syn_psl.vhdl
+grep -q "gate_anyconst" syn_psl.vhdl
+
+synth --std=08 exp_vhd.vhdl -e > syn_vhd.vhdl
+grep -q "gate_anyconst" syn_vhd.vhdl
+
+echo "Test successful"