3 files changed, 51 insertions, 0 deletions
diff --git a/testsuite/gna/issue450/cocotb/Makefile b/testsuite/gna/issue450/cocotb/Makefile
new file mode 100644
index 000000000..e740fd2a2
--- /dev/null
+++ b/testsuite/gna/issue450/cocotb/Makefile
@@ -0,0 +1,17 @@
+CWD = $(shell pwd)
+COCOTB = $(CWD)/../../..
+
+TOPLEVEL_LANG = vhdl
+
+VHDL_SOURCES = $(CWD)/../hdl/top.vhd
+
+SIM = ghdl
+CMD_BIN = ghdl
+
+TOPLEVEL=top
+MODULE=$(TOPLEVEL)_cocotb
+
+include $(COCOTB)/makefiles/Makefile.inc
+include $(COCOTB)/makefiles/Makefile.sim
+
+sim: $(MODULE).py
diff --git a/testsuite/gna/issue450/cocotb/top.vhd b/testsuite/gna/issue450/cocotb/top.vhd
new file mode 100644
index 000000000..e53cea9ea
--- /dev/null
+++ b/testsuite/gna/issue450/cocotb/top.vhd
@@ -0,0 +1,22 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity top is
+    port ( 
+        clk : in std_logic;
+        A : in std_logic_vector(4 downto 1);
+        B : out std_logic_vector(4 downto 1)
+    );
+end top;
+
+architecture rtl of top is
+begin
+    gen_pe : for i in 1 to 4 generate
+        test : process (clk) is
+        begin
+            if (rising_edge(clk)) then 
+                B(i) <= A(i);
+            end if;
+        end process test;
+    end generate gen_pe;
+end rtl;
diff --git a/testsuite/gna/issue450/cocotb/top_cocotb.py b/testsuite/gna/issue450/cocotb/top_cocotb.py
new file mode 100644
index 000000000..2f30e0e2a
--- /dev/null
+++ b/testsuite/gna/issue450/cocotb/top_cocotb.py
@@ -0,0 +1,12 @@
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import Timer
+
+@cocotb.test()
+def test_gen(dut):
+    cocotb.fork(Clock(dut.clk, 1000).start())
+
+    yield Timer(1000)
+
+    for i in dut:       
+        print i._log.info("Found something: %s" % i._fullname)