diff options
-rw-r--r-- | testsuite/gna/issue1834/repro1.vhdl | 18 | ||||
-rw-r--r-- | testsuite/gna/issue1834/tb.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/gna/issue1834/testsuite.sh | 12 |
3 files changed, 59 insertions, 0 deletions
diff --git a/testsuite/gna/issue1834/repro1.vhdl b/testsuite/gna/issue1834/repro1.vhdl new file mode 100644 index 000000000..7f2bb205e --- /dev/null +++ b/testsuite/gna/issue1834/repro1.vhdl @@ -0,0 +1,18 @@ +entity repro1 is +end; + +architecture a of repro1 is +begin + process + begin + -- Over int'high + for i in integer'high to integer'high+1 loop + end loop; + + -- Under int'low + for i in integer'low downto integer'low-1 loop + end loop; + + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue1834/tb.vhdl b/testsuite/gna/issue1834/tb.vhdl new file mode 100644 index 000000000..29258b948 --- /dev/null +++ b/testsuite/gna/issue1834/tb.vhdl @@ -0,0 +1,29 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity tb is +end entity; +architecture a of tb is + signal clk : std_logic := '0'; + signal running : boolean := true; +begin + clk <= not clk after 5 ns when running else '0'; + + process(clk) + -- This assignment one throws a proper error message: + --constant var : integer := integer'high+1; + begin + if(rising_edge(clk)) then + -- Looping out of integer range results in Bug-Message + + -- Over int'high + for i in integer'high to integer'high+1 loop + end loop; + + -- Under int'low + for i in integer'low downto integer'low-1 loop + end loop; + running <= false; + end if; + end process; +end architecture; diff --git a/testsuite/gna/issue1834/testsuite.sh b/testsuite/gna/issue1834/testsuite.sh new file mode 100755 index 000000000..f0a87ab4c --- /dev/null +++ b/testsuite/gna/issue1834/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure -Werror tb.vhdl + +analyze tb.vhdl +elab_simulate_failure tb + +clean + +echo "Test successful" |