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-rw-r--r--doc/using/UART_srcs/file_in_out/Zeichnung.svg290
-rw-r--r--doc/using/UART_srcs/file_in_out/makefile13
-rw-r--r--doc/using/UART_srcs/file_in_out/tb_file.vhd142
-rw-r--r--doc/using/UART_srcs/file_in_out/test.txt1
-rw-r--r--doc/using/UART_srcs/file_in_out/test1.txt1
-rw-r--r--doc/using/UART_srcs/file_in_out/zeichnung.pngbin0 -> 11280 bytes
6 files changed, 447 insertions, 0 deletions
diff --git a/doc/using/UART_srcs/file_in_out/Zeichnung.svg b/doc/using/UART_srcs/file_in_out/Zeichnung.svg
new file mode 100644
index 000000000..ae9e85d86
--- /dev/null
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diff --git a/doc/using/UART_srcs/file_in_out/makefile b/doc/using/UART_srcs/file_in_out/makefile
new file mode 100644
index 000000000..e7ee72400
--- /dev/null
+++ b/doc/using/UART_srcs/file_in_out/makefile
@@ -0,0 +1,13 @@
+all:
+ rm -rf work
+ mkdir work
+
+ ghdl -a --work=work --workdir=work ../capitalisation/capitalisation.vhd
+ ghdl -a --work=work --workdir=work tb_file.vhd
+ ghdl -e --ieee=synopsys -fexplicit --workdir=work -Pwork tb_file
+ ghdl -r tb_file --wave=tbench.ghw --stop-time=200us
+
+
+view:
+ gtkwave tbench.ghw a.gtkw
+
diff --git a/doc/using/UART_srcs/file_in_out/tb_file.vhd b/doc/using/UART_srcs/file_in_out/tb_file.vhd
new file mode 100644
index 000000000..fe18f6665
--- /dev/null
+++ b/doc/using/UART_srcs/file_in_out/tb_file.vhd
@@ -0,0 +1,142 @@
+--tb_file.vhd
+------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_file IS
+END tb_file;
+--vhdl no seek or rewind function in VHDL
+
+ARCHITECTURE behavior OF tb_file IS
+
+signal clk : std_logic := '0';
+signal reset : std_logic;
+
+signal rdata : std_logic_vector(7 downto 0);
+signal rd_en : std_logic;
+signal rd : std_logic;
+
+signal wdata : std_logic_vector(7 downto 0);
+signal wr_en : std_logic:='1';
+signal wr : std_logic;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+component capitalisation is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --in
+ rdata : in std_logic_vector(7 downto 0);
+ rd_en : in std_logic;
+ rd : out std_logic;
+ --out
+ wdata : out std_logic_vector(7 downto 0);
+ wr_en : in std_logic;
+ wr : out std_logic
+ );
+end component;
+
+ -- Clock period definitions
+ constant clk_period : time := 10 ns;
+
+subtype by_te is character;
+type f_byte is file of by_te;
+
+BEGIN
+
+process(clk)
+begin
+ if rising_edge (clk) then
+ if reset='0' then
+ wr_en<='1';
+ else
+ wr_en<='0';
+ end if;
+ end if;
+end process;
+
+--read a file
+process (reset,clk)
+constant file_name: string:="test.txt";
+file in_file: f_byte open read_mode is file_name;
+
+variable a:character;
+
+begin
+ if reset='1' then
+ rd_en<='0';
+ else
+
+ if rising_edge(clk) then
+ if rd_en='0' or rd='1' then
+ if not endfile (in_file) then
+ read(in_file,a);
+ rdata<=std_logic_vector(to_unsigned(character'pos(a),8));
+ --very tricky the conversation
+ rd_en<='1';
+ else
+ rd_en<='0';
+ end if;
+ end if;
+ end if;
+ --wait until rising_edge(CLK) and rd='1';
+ end if;
+end process;
+
+
+
+--write a file
+process (clk)
+constant file_name: string:="test1.txt";
+file out_file: f_byte open write_mode is file_name;
+
+----variable in_line,out_line: line;
+variable b:character;
+
+ begin
+ if rising_edge(CLK) then
+ if reset='0' then
+ if wr='1' then
+ b:=character'val(to_integer(unsigned(wdata)));
+ write(out_file,b);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ stim_proc : process
+ begin
+ reset <= '1';
+
+ wait for 50 ns;
+ reset <='0';
+
+ wait;
+ end process;
+
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+engine: capitalisation
+ port map(
+
+ clk => clk,
+ reset => reset,
+
+ rdata => rdata,
+ rd_en => rd_en,
+ rd => rd,
+
+ wdata => wdata,
+ wr_en => wr_en,
+ wr => wr
+ );
+
+
+END;
diff --git a/doc/using/UART_srcs/file_in_out/test.txt b/doc/using/UART_srcs/file_in_out/test.txt
new file mode 100644
index 000000000..3ee58d9a3
--- /dev/null
+++ b/doc/using/UART_srcs/file_in_out/test.txt
@@ -0,0 +1 @@
+Hallo world! Can you see my text?
diff --git a/doc/using/UART_srcs/file_in_out/test1.txt b/doc/using/UART_srcs/file_in_out/test1.txt
new file mode 100644
index 000000000..a868f3f93
--- /dev/null
+++ b/doc/using/UART_srcs/file_in_out/test1.txt
@@ -0,0 +1 @@
+HALLO WORLD! CAN YOU SEE MY TEXT?
diff --git a/doc/using/UART_srcs/file_in_out/zeichnung.png b/doc/using/UART_srcs/file_in_out/zeichnung.png
new file mode 100644
index 000000000..e849417f4
--- /dev/null
+++ b/doc/using/UART_srcs/file_in_out/zeichnung.png
Binary files differ
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-25 13:13:06 +0000