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-rw-r--r--testsuite/gna/issue381/test.vhdl14
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/gna/issue381/test.vhdl b/testsuite/gna/issue381/test.vhdl
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+++ b/testsuite/gna/issue381/test.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity can_rx is
+ port (
+ demo : in std_logic;
+ status : out std_logic_vector (31 downto 0)
+ );
+end can_rx;
+
+architecture rtl of can_rx is
+begin
+ status(0) <= (0=>'0', others => '0') when demo = '1' else (0=>'1', others => '0');
+end rtl;