diff options
Diffstat (limited to 'testsuite/gna/issue50/vector.d')
90 files changed, 6959 insertions, 0 deletions
diff --git a/testsuite/gna/issue50/vector.d/add_118.vhd b/testsuite/gna/issue50/vector.d/add_118.vhd new file mode 100644 index 000000000..9134bc04d --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_118.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_118 is + port ( + result : out std_logic_vector(15 downto 0); + in_a : in std_logic_vector(15 downto 0); + in_b : in std_logic_vector(15 downto 0) + ); +end add_118; + +architecture augh of add_118 is + + signal carry_inA : std_logic_vector(17 downto 0); + signal carry_inB : std_logic_vector(17 downto 0); + signal carry_res : std_logic_vector(17 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(16 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/add_134.vhd b/testsuite/gna/issue50/vector.d/add_134.vhd new file mode 100644 index 000000000..4f33da61f --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_134.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_134 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); +end add_134; + +architecture augh of add_134 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(32 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/add_170.vhd b/testsuite/gna/issue50/vector.d/add_170.vhd new file mode 100644 index 000000000..dc7f53489 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_170.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_170 is + port ( + result : out std_logic_vector(8 downto 0); + in_a : in std_logic_vector(8 downto 0); + in_b : in std_logic_vector(8 downto 0) + ); +end add_170; + +architecture augh of add_170 is + + signal carry_inA : std_logic_vector(10 downto 0); + signal carry_inB : std_logic_vector(10 downto 0); + signal carry_res : std_logic_vector(10 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(9 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/add_171.vhd b/testsuite/gna/issue50/vector.d/add_171.vhd new file mode 100644 index 000000000..82b3708ec --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_171.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_171 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); +end add_171; + +architecture augh of add_171 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(32 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/add_188.vhd b/testsuite/gna/issue50/vector.d/add_188.vhd new file mode 100644 index 000000000..4bb414f53 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_188.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_188 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); +end add_188; + +architecture augh of add_188 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(32 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/add_214.vhd b/testsuite/gna/issue50/vector.d/add_214.vhd new file mode 100644 index 000000000..97020f26b --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_214.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_214 is + port ( + result : out std_logic_vector(7 downto 0); + in_a : in std_logic_vector(7 downto 0); + in_b : in std_logic_vector(7 downto 0) + ); +end add_214; + +architecture augh of add_214 is + + signal carry_inA : std_logic_vector(9 downto 0); + signal carry_inB : std_logic_vector(9 downto 0); + signal carry_res : std_logic_vector(9 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(8 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/add_220.vhd b/testsuite/gna/issue50/vector.d/add_220.vhd new file mode 100644 index 000000000..b527a5d81 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/add_220.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_220 is + port ( + result : out std_logic_vector(15 downto 0); + in_a : in std_logic_vector(15 downto 0); + in_b : in std_logic_vector(15 downto 0) + ); +end add_220; + +architecture augh of add_220 is + + signal carry_inA : std_logic_vector(17 downto 0); + signal carry_inB : std_logic_vector(17 downto 0); + signal carry_res : std_logic_vector(17 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(16 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/assert_uut.vhd b/testsuite/gna/issue50/vector.d/assert_uut.vhd new file mode 100644 index 000000000..b097652a9 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/assert_uut.vhd @@ -0,0 +1,169 @@ +--test bench written by Alban Bourge @ TIMA +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkg_tb.all; + +entity assert_uut is + port( + clock : in std_logic; + reset : in std_logic; + context_uut : in context_t; + en_feed : in std_logic; + stdin_rdy : in std_logic; + stdin_ack : out std_logic; + stdin_data : out stdin_vector; + en_check : in std_logic; + stdout_rdy : in std_logic; + stdout_ack : out std_logic; + stdout_data : in stdout_vector; + vecs_found : out std_logic; + vec_read : out std_logic; + n_error : out std_logic + ); +end assert_uut; + +architecture rtl of assert_uut is + + type vin_table is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector; + type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector; + constant input_vectors_1 : vin_table := ( + --##INPUT_VECTORS_1_GO_DOWN_HERE##-- + 0 => x"00_00_00_07", + 1 => x"00_00_00_03", + --##INPUT_VECTORS_1_GO_OVER_HERE##-- + others => (others => '0')); + constant output_vectors_1 : vout_table := ( + --##OUTPUT_VECTORS_1_GO_DOWN_HERE##-- + 0 => x"00_00_00_16", + --##OUTPUT_VECTORS_1_GO_OVER_HERE##-- + others => (others => '0')); + constant input_vectors_2 : vin_table := ( + --##INPUT_VECTORS_2_GO_DOWN_HERE##-- + 0 => x"00_00_00_07", + 1 => x"00_00_00_03", + --##INPUT_VECTORS_2_GO_OVER_HERE##-- + others => (others => '0')); + constant output_vectors_2 : vout_table := ( + --##OUTPUT_VECTORS_2_GO_DOWN_HERE##-- + 0 => x"00_00_00_16", + --##OUTPUT_VECTORS_2_GO_OVER_HERE##-- + others => (others => '0')); + + signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0); + signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0); + signal stdin_ack_sig : std_logic; + signal vector_read : std_logic; + +begin + + feed : process(reset, clock) is + variable in_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0); + variable in_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0); + begin + if (reset = '1') then + in_vec_counter_1 := (others => '0'); + in_vec_counter_2 := (others => '0'); + stdin_data <= (others => '0'); + stdin_ack_sig <= '0'; + elsif rising_edge(clock) then + case context_uut is + when "01" => + if (en_feed = '1') then + stdin_data <= input_vectors_1(to_integer(in_vec_counter_1)); + stdin_ack_sig <= '1'; + if (stdin_rdy = '1' and stdin_ack_sig = '1') then + in_vec_counter_1 := in_vec_counter_1 + 1; + stdin_ack_sig <= '0'; + end if; + else + --in_vec_counter_1 <= (others => '0'); + stdin_data <= (others => '0'); + stdin_ack_sig <= '0'; + end if; + when "10" => + if (en_feed = '1') then + stdin_data <= input_vectors_2(to_integer(in_vec_counter_2)); + stdin_ack_sig <= '1'; + if (stdin_rdy = '1' and stdin_ack_sig = '1') then + in_vec_counter_2 := in_vec_counter_2 + 1; + stdin_ack_sig <= '0'; + end if; + else + --in_vec_counter_2 <= (others => '0'); + stdin_data <= (others => '0'); + stdin_ack_sig <= '0'; + end if; + when others => + end case; + end if; + end process feed; + + check : process(reset, clock) is + begin + if (reset = '1') then + n_error <= '1'; + vec_read <= '0'; + elsif rising_edge(clock) then + vec_read <= '0'; + if (en_check = '1') then + if (stdout_rdy = '1') then + vec_read <= '1'; + case context_uut is + when "01" => + assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1))) + report "ERROR ---> Bad output vector found"; + --synthesizable check + if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then + n_error <= '0'; + end if; + when "10" => + assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2))) + report "ERROR ---> Bad output vector found"; + --synthesizable check + if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then + n_error <= '0'; + end if; + when others => + end case; + end if; + end if; + end if; + end process check; + + read_counter : process(reset, clock) is + begin + if (reset = '1') then + out_vec_counter_1 <= (others => '0'); + out_vec_counter_2 <= (others => '0'); + elsif rising_edge(clock) then + if (en_check = '1') then + if (stdout_rdy = '1') then + case context_uut is + when "01" => + out_vec_counter_1 <= out_vec_counter_1 + 1; + when "10" => + out_vec_counter_2 <= out_vec_counter_2 + 1; + when others => + end case; + end if; + --else + -- case context_uut is + -- when "01" => + -- out_vec_counter_1 <= (others => '0'); + -- when "10" => + -- out_vec_counter_2 <= (others => '0'); + -- when others => + -- end case; + end if; + end if; + end process read_counter; + + --asynchronous declarations + stdout_ack <= en_check; + stdin_ack <= stdin_ack_sig; + vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0'; + +end rtl; diff --git a/testsuite/gna/issue50/vector.d/cmp_111.vhd b/testsuite/gna/issue50/vector.d/cmp_111.vhd new file mode 100644 index 000000000..5e35d5292 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_111.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_111 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_111; + +architecture augh of cmp_111 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_112.vhd b/testsuite/gna/issue50/vector.d/cmp_112.vhd new file mode 100644 index 000000000..e27456ee4 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_112.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_112 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_112; + +architecture augh of cmp_112 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_113.vhd b/testsuite/gna/issue50/vector.d/cmp_113.vhd new file mode 100644 index 000000000..f83b71ce1 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_113.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_113 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_113; + +architecture augh of cmp_113 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_114.vhd b/testsuite/gna/issue50/vector.d/cmp_114.vhd new file mode 100644 index 000000000..e15bf43cd --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_114.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_114 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_114; + +architecture augh of cmp_114 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_115.vhd b/testsuite/gna/issue50/vector.d/cmp_115.vhd new file mode 100644 index 000000000..00d218957 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_115.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_115 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_115; + +architecture augh of cmp_115 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_119.vhd b/testsuite/gna/issue50/vector.d/cmp_119.vhd new file mode 100644 index 000000000..2b2245787 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_119.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_119 is + port ( + ne : out std_logic; + in0 : in std_logic_vector(15 downto 0); + in1 : in std_logic_vector(15 downto 0) + ); +end cmp_119; + +architecture augh of cmp_119 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_126.vhd b/testsuite/gna/issue50/vector.d/cmp_126.vhd new file mode 100644 index 000000000..f2a630842 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_126.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_126 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_126; + +architecture augh of cmp_126 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_127.vhd b/testsuite/gna/issue50/vector.d/cmp_127.vhd new file mode 100644 index 000000000..94611a018 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_127.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_127 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_127; + +architecture augh of cmp_127 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_128.vhd b/testsuite/gna/issue50/vector.d/cmp_128.vhd new file mode 100644 index 000000000..d23132fd4 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_128.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_128 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_128; + +architecture augh of cmp_128 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_129.vhd b/testsuite/gna/issue50/vector.d/cmp_129.vhd new file mode 100644 index 000000000..cc56d03b8 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_129.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_129 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_129; + +architecture augh of cmp_129 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_130.vhd b/testsuite/gna/issue50/vector.d/cmp_130.vhd new file mode 100644 index 000000000..6e3e529eb --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_130.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_130 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_130; + +architecture augh of cmp_130 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_131.vhd b/testsuite/gna/issue50/vector.d/cmp_131.vhd new file mode 100644 index 000000000..c7450e430 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_131.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_131 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_131; + +architecture augh of cmp_131 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_132.vhd b/testsuite/gna/issue50/vector.d/cmp_132.vhd new file mode 100644 index 000000000..12cbe3918 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_132.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_132 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_132; + +architecture augh of cmp_132 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_133.vhd b/testsuite/gna/issue50/vector.d/cmp_133.vhd new file mode 100644 index 000000000..efee40dc7 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_133.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_133 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_133; + +architecture augh of cmp_133 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_135.vhd b/testsuite/gna/issue50/vector.d/cmp_135.vhd new file mode 100644 index 000000000..d5e1d49e3 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_135.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_135 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_135; + +architecture augh of cmp_135 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_136.vhd b/testsuite/gna/issue50/vector.d/cmp_136.vhd new file mode 100644 index 000000000..1dfb02bc3 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_136.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_136 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_136; + +architecture augh of cmp_136 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_137.vhd b/testsuite/gna/issue50/vector.d/cmp_137.vhd new file mode 100644 index 000000000..064415f94 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_137.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_137 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_137; + +architecture augh of cmp_137 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_138.vhd b/testsuite/gna/issue50/vector.d/cmp_138.vhd new file mode 100644 index 000000000..c5f42eaa5 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_138.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_138 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_138; + +architecture augh of cmp_138 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_139.vhd b/testsuite/gna/issue50/vector.d/cmp_139.vhd new file mode 100644 index 000000000..809619fbf --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_139.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_139 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_139; + +architecture augh of cmp_139 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_140.vhd b/testsuite/gna/issue50/vector.d/cmp_140.vhd new file mode 100644 index 000000000..033dd940a --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_140.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_140 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_140; + +architecture augh of cmp_140 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_141.vhd b/testsuite/gna/issue50/vector.d/cmp_141.vhd new file mode 100644 index 000000000..f514e59d4 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_141.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_141 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_141; + +architecture augh of cmp_141 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_142.vhd b/testsuite/gna/issue50/vector.d/cmp_142.vhd new file mode 100644 index 000000000..8e618fb9b --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_142.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_142 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_142; + +architecture augh of cmp_142 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_146.vhd b/testsuite/gna/issue50/vector.d/cmp_146.vhd new file mode 100644 index 000000000..56262f16c --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_146.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_146 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_146; + +architecture augh of cmp_146 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_148.vhd b/testsuite/gna/issue50/vector.d/cmp_148.vhd new file mode 100644 index 000000000..de5f67862 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_148.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_148 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_148; + +architecture augh of cmp_148 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_150.vhd b/testsuite/gna/issue50/vector.d/cmp_150.vhd new file mode 100644 index 000000000..75c66f25a --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_150.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_150 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_150; + +architecture augh of cmp_150 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_152.vhd b/testsuite/gna/issue50/vector.d/cmp_152.vhd new file mode 100644 index 000000000..4d05e52bf --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_152.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_152 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_152; + +architecture augh of cmp_152 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_154.vhd b/testsuite/gna/issue50/vector.d/cmp_154.vhd new file mode 100644 index 000000000..b9dde5333 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_154.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_154 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_154; + +architecture augh of cmp_154 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_156.vhd b/testsuite/gna/issue50/vector.d/cmp_156.vhd new file mode 100644 index 000000000..75cf950bd --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_156.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_156 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_156; + +architecture augh of cmp_156 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_158.vhd b/testsuite/gna/issue50/vector.d/cmp_158.vhd new file mode 100644 index 000000000..82efe368c --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_158.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_158 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_158; + +architecture augh of cmp_158 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_160.vhd b/testsuite/gna/issue50/vector.d/cmp_160.vhd new file mode 100644 index 000000000..9fb84d1cd --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_160.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_160 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_160; + +architecture augh of cmp_160 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_174.vhd b/testsuite/gna/issue50/vector.d/cmp_174.vhd new file mode 100644 index 000000000..86a3b443b --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_174.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_174 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_174; + +architecture augh of cmp_174 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_176.vhd b/testsuite/gna/issue50/vector.d/cmp_176.vhd new file mode 100644 index 000000000..9ba5527e2 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_176.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_176 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_176; + +architecture augh of cmp_176 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_178.vhd b/testsuite/gna/issue50/vector.d/cmp_178.vhd new file mode 100644 index 000000000..f594227ac --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_178.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_178 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_178; + +architecture augh of cmp_178 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_180.vhd b/testsuite/gna/issue50/vector.d/cmp_180.vhd new file mode 100644 index 000000000..b69344eec --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_180.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_180 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_180; + +architecture augh of cmp_180 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_183.vhd b/testsuite/gna/issue50/vector.d/cmp_183.vhd new file mode 100644 index 000000000..3fea5412e --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_183.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_183 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_183; + +architecture augh of cmp_183 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_185.vhd b/testsuite/gna/issue50/vector.d/cmp_185.vhd new file mode 100644 index 000000000..e45f5ca03 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_185.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_185 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_185; + +architecture augh of cmp_185 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_187.vhd b/testsuite/gna/issue50/vector.d/cmp_187.vhd new file mode 100644 index 000000000..4254b67ab --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_187.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_187 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_187; + +architecture augh of cmp_187 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_191.vhd b/testsuite/gna/issue50/vector.d/cmp_191.vhd new file mode 100644 index 000000000..af123383f --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_191.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_191 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_191; + +architecture augh of cmp_191 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_193.vhd b/testsuite/gna/issue50/vector.d/cmp_193.vhd new file mode 100644 index 000000000..3eeeba859 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_193.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_193 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_193; + +architecture augh of cmp_193 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_195.vhd b/testsuite/gna/issue50/vector.d/cmp_195.vhd new file mode 100644 index 000000000..61851b275 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_195.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_195 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_195; + +architecture augh of cmp_195 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_198.vhd b/testsuite/gna/issue50/vector.d/cmp_198.vhd new file mode 100644 index 000000000..6620b9de3 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_198.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_198 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_198; + +architecture augh of cmp_198 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_200.vhd b/testsuite/gna/issue50/vector.d/cmp_200.vhd new file mode 100644 index 000000000..794a2ddad --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_200.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_200 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_200; + +architecture augh of cmp_200 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_202.vhd b/testsuite/gna/issue50/vector.d/cmp_202.vhd new file mode 100644 index 000000000..a16cc719a --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_202.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_202 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_202; + +architecture augh of cmp_202 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_204.vhd b/testsuite/gna/issue50/vector.d/cmp_204.vhd new file mode 100644 index 000000000..18c2cade8 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_204.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_204 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_204; + +architecture augh of cmp_204 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_215.vhd b/testsuite/gna/issue50/vector.d/cmp_215.vhd new file mode 100644 index 000000000..2671110bd --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_215.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_215 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_215; + +architecture augh of cmp_215 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_216.vhd b/testsuite/gna/issue50/vector.d/cmp_216.vhd new file mode 100644 index 000000000..37307f2b6 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_216.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_216 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_216; + +architecture augh of cmp_216 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_217.vhd b/testsuite/gna/issue50/vector.d/cmp_217.vhd new file mode 100644 index 000000000..ca2756b70 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_217.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_217 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_217; + +architecture augh of cmp_217 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_218.vhd b/testsuite/gna/issue50/vector.d/cmp_218.vhd new file mode 100644 index 000000000..09b8d9273 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_218.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_218 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); +end cmp_218; + +architecture augh of cmp_218 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cmp_221.vhd b/testsuite/gna/issue50/vector.d/cmp_221.vhd new file mode 100644 index 000000000..6c7aaac74 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cmp_221.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_221 is + port ( + ne : out std_logic; + in0 : in std_logic_vector(15 downto 0); + in1 : in std_logic_vector(15 downto 0) + ); +end cmp_221; + +architecture augh of cmp_221 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in0 /= in1 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/cp3_test.vhd b/testsuite/gna/issue50/vector.d/cp3_test.vhd new file mode 100644 index 000000000..99fdbb678 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/cp3_test.vhd @@ -0,0 +1,280 @@ +-- written by Alban Bourge @ TIMA +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkg_tb.all; + +entity cp3_test is + port( + clock : in std_logic; + reset : in std_logic; + n_error : out std_logic; + stopped : out std_logic + ); +end cp3_test; + +architecture rtl of cp3_test is + + --TOP signals + signal reset_top : std_logic := '0'; + signal stdin_data : stdin_vector; + signal stdin_rdy : std_logic; + signal stdin_ack : std_logic; + signal stdout_data : stdout_vector; + signal stdout_rdy : std_logic; + signal stdout_ack : std_logic; + --ASSERT_UNIT signals + signal context_uut : context_t; + signal en_feed : std_logic; + signal en_check : std_logic; + signal n_error_s : std_logic; + signal vecs_found : std_logic; + signal vec_read : std_logic; + --PROG unit signals + signal instr_next : instruction; + -- FSM unit signals + signal step : std_logic; + signal start : std_logic; + -- FSM signals + signal reset_fsm : std_logic; + signal stopped_s : std_logic; + + +-------------------------------------- +-- PART OF ARCHITECTURE WITH CP3 -- + + --TOP signals + signal cp_en : std_logic := '0'; + signal cp_rest : std_logic := '0'; + signal cp_ok : std_logic; + signal cp_din : cp_vector := (others => '0'); + signal cp_dout : cp_vector; + --RAM signals + signal ram_1 : ram_instruction; + signal ram_2 : ram_instruction; + signal address1 : std_logic_vector(12 downto 0) := (others => '0'); + signal address2 : std_logic_vector(12 downto 0) := (others => '0'); + signal datain : cp_vector := (others => '0'); + signal dout1 : cp_vector; + signal dout2 : cp_vector; + + --dut component declaration + component top is + port ( + clock : in std_logic; + reset : in std_logic; + start : in std_logic; + stdin_data : in stdin_vector; + stdin_rdy : out std_logic; + stdin_ack : in std_logic; + stdout_data : out stdout_vector; + stdout_rdy : out std_logic; + stdout_ack : in std_logic; + cp_en : in std_logic; + cp_rest : in std_logic; + cp_din : in cp_vector; + cp_dout : out cp_vector; + cp_ok : out std_logic + ); + end component top; + +begin + + uut : entity work.top(augh) + port map( + clock => clock, + reset => reset_top, + start => start, + stdin_data => stdin_data, + stdin_rdy => stdin_rdy, + stdin_ack => stdin_ack, + cp_en => cp_en, + cp_rest => cp_rest, + cp_ok => cp_ok, + cp_din => cp_din, + cp_dout => cp_dout, + stdout_data => stdout_data, + stdout_rdy => stdout_rdy, + stdout_ack => stdout_ack + ); + + ram1 : entity work.sync_ram(rtl) + port map( + clock => clock, + we => ram_1.we, + address => address1, + datain => datain, + dataout => dout1 + ); + + ram2 : entity work.sync_ram(rtl) + port map( + clock => clock, + we => ram_2.we, + address => address2, + datain => datain, + dataout => dout2 + ); + + fsm_unit : entity work.fsm(rtl) + port map( + clock => clock, + reset => reset, + --prog interface + instr_next => instr_next, + step => step, + --uut interface + cp_ok => cp_ok, + stdin_rdy => stdin_rdy, + stdin_ack => stdin_ack, + reset_fsm => reset_fsm, + start => start, + cp_en => cp_en, + cp_rest => cp_rest, + --ram interface + ram_1 => ram_1, + ram_2 => ram_2, + --assert_uut interface + context_uut => context_uut, + en_feed => en_feed, + en_check => en_check, + vecs_found => vecs_found, + vec_read => vec_read, + --tb interface + stopped => stopped_s + ); + + --RAM ADDRESS controller 1 + ram_ctrl1 : process(clock, reset) + begin + if (reset = '1') then + address1 <= (others => '0'); + elsif rising_edge(clock) then + if (ram_1.addr_z = '1') then + address1 <= (others => '0'); + elsif (ram_1.addr_up = '1') then + address1 <= std_logic_vector(unsigned(address1) + 1); + end if; + end if; + end process ram_ctrl1; + + --RAM ADDRESS controller 2 + ram_ctrl2 : process(clock, reset) + begin + if (reset = '1') then + address2 <= (others => '0'); + elsif rising_edge(clock) then + if (ram_2.addr_z = '1') then + address2 <= (others => '0'); + elsif (ram_2.addr_up = '1') then + address2 <= std_logic_vector(unsigned(address2) + 1); + end if; + end if; + end process ram_ctrl2; + + --other comb signals + datain <= cp_dout; + cp_din <= dout2 when ram_2.sel = '1' else dout1; + +-- END OF ARCHITECTURE WITH CP3 -- +-------------------------------------- + +-------------------------------------- +-- PART OF ARCHITECTURE WITHOUT CP3 -- +-- +-- --dut component declaration +-- component top is +-- port ( +-- clock : in std_logic; +-- reset : in std_logic; +-- start : in std_logic; +-- stdin_data : in stdin_vector; +-- stdin_rdy : out std_logic; +-- stdin_ack : in std_logic; +-- stdout_data : out stdout_vector; +-- stdout_rdy : out std_logic; +-- stdout_ack : in std_logic +-- ); +-- end component top; +-- +--begin +-- +-- uut : entity work.top(augh) +-- port map( +-- clock => clock, +-- reset => reset_top, +-- start => start, +-- stdin_data => stdin_data, +-- stdin_rdy => stdin_rdy, +-- stdin_ack => stdin_ack, +-- stdout_data => stdout_data, +-- stdout_rdy => stdout_rdy, +-- stdout_ack => stdout_ack +-- ); +-- +-- fsm_unit : entity work.fsm(rtl) +-- port map( +-- clock => clock, +-- reset => reset, +-- --prog interface +-- instr_next => instr_next, +-- step => step, +-- --uut interface +-- cp_ok => '0', +-- stdin_rdy => stdin_rdy, +-- stdin_ack => stdin_ack, +-- reset_fsm => reset_fsm, +-- start => start, +-- cp_en => open, +-- cp_rest => open, +-- --ram interface +-- ram_1 => open, +-- ram_2 => open, +-- --assert_uut interface +-- context_uut => context_uut, +-- en_feed => en_feed, +-- en_check => en_check, +-- vecs_found => vecs_found, +-- vec_read => vec_read, +-- --tb interface +-- stopped => stopped_s +-- ); +-- +-- END OF ARCHITECTURE WITHOUT CP3 -- +-------------------------------------- + + assert_unit : entity work.assert_uut(rtl) + port map( + clock => clock, + reset => reset, + context_uut => context_uut, + en_feed => en_feed, + stdin_rdy => stdin_rdy, + stdin_ack => stdin_ack, + stdin_data => stdin_data, + en_check => en_check, + stdout_rdy => stdout_rdy, + stdout_ack => stdout_ack, + stdout_data => stdout_data, + vecs_found => vecs_found, + vec_read => vec_read, + n_error => n_error_s + ); + + prog_unit : entity work.prog(rtl) + port map( + clock => clock, + reset => reset, + step => step, + instr_next => instr_next + ); + + --other comb signals + reset_top <= reset or reset_fsm; + + --outputs + n_error <= n_error_s; + stopped <= stopped_s; + +end rtl; diff --git a/testsuite/gna/issue50/vector.d/fsm.vhd b/testsuite/gna/issue50/vector.d/fsm.vhd new file mode 100644 index 000000000..2f4ef87ee --- /dev/null +++ b/testsuite/gna/issue50/vector.d/fsm.vhd @@ -0,0 +1,396 @@ +--test bench written by Alban Bourge @ TIMA +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkg_tb.all; + +entity fsm is + port( + clock : in std_logic; + reset : in std_logic; + --prog interface + instr_next : in instruction; + step : out std_logic; + --uut interface + cp_ok : in std_logic; + stdin_rdy : in std_logic; + stdin_ack : in std_logic; + reset_fsm : out std_logic; + start : out std_logic; + cp_en : out std_logic; + cp_rest : out std_logic; + --ram interface + ram_1 : out ram_instruction; + ram_2 : out ram_instruction; + --assert_uut interface + context_uut : out context_t; + en_feed : out std_logic; + en_check : out std_logic; + vecs_found : in std_logic; + vec_read : in std_logic; + --tb interface + stopped : out std_logic + ); +end fsm; + +architecture rtl of fsm is + + -- read output + signal step_sig : std_logic; + -- FSM signals + signal instr_c : instruction := instr_rst; + signal instr_n : instruction := instr_rst; + -- TIMER signal + signal times_en : std_logic := '0'; + signal times_z : std_logic := '0'; + signal times : unsigned(ARG_WIDTH - 1 downto 0); + signal times_max : unsigned(ARG_WIDTH - 1 downto 0); + signal times_ok : std_logic := '0'; + -- COUNTER signal + signal count_en : std_logic := '0'; + signal count_z : std_logic := '0'; + signal count : unsigned(ARG_WIDTH - 1 downto 0); + signal count_max : unsigned(ARG_WIDTH - 1 downto 0); + signal count_ok : std_logic := '0'; + -- runtime counter + signal runtime_en : std_logic := '0'; + signal runtime : integer range 0 to 99999999; --100 million cycles + +begin + + -- FSM + state_reg : process (clock, reset) is + begin + if (reset = '1') then + instr_c <= instr_rst; + elsif rising_edge(clock) then + instr_c <= instr_n; + end if; + end process state_reg; + + comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read) + begin + --default definition for fsm control signals + instr_n <= instr_rst; + step_sig <= '0'; + --top + reset_fsm <= '0'; + start <= '0'; + cp_en <= '0'; + cp_rest <= '0'; + --counter & timer + times_en <= '0'; + times_max <= (others => '0'); + count_en <= '0'; + count_max <= (others => '0'); + --runtime counter + runtime_en <= '0'; + --ram + ram_1 <= ram_instr_z; + ram_2 <= ram_instr_z; + --assert_uut + en_feed <= '0'; + en_check <= '0'; + --tb interface + stopped <= '0'; + + case instr_c.state is + when Rst => + --signals + reset_fsm <= '1'; + ram_1.addr_z <= '1'; + ram_2.addr_z <= '1'; + step_sig <= '1'; --demand for next instruction + --transition + instr_n <= instr_next; + + when Sig_start => + --signals + start <= '1'; + step_sig <= '1'; --demand for next instruction + --transition + instr_n <= instr_next; + --if (instr_next.state = Ack_data) then + --en_feed <= '1'; + --end if; + + when Ack_data => + times_max <= instr_c.arg - 1; + --signals + en_feed <= '1'; + --transition + if (stdin_rdy = '1' and stdin_ack = '1') then + times_en <= '1'; + end if; + if (times_ok = '1') then + en_feed <= '0'; + step_sig <= '1'; + instr_n <= instr_next; + else + instr_n <= instr_c; + end if; + + when Running => + --signals + count_max <= instr_c.arg; + count_en <= '1'; + --en_check <= '1'; + --runtime counter + if(vecs_found = '0') then + runtime_en <= '1'; + end if; + --transition + if (count_ok = '1') then + step_sig <= '1'; + instr_n <= instr_next; + else + instr_n <= instr_c; + end if; + + when Waitfor => + --signals + count_max <= instr_c.arg; + en_check <= '1'; + if(vec_read = '1') then + count_en <= '1'; + end if; + --runtime counter + if(vecs_found = '0') then + runtime_en <= '1'; + end if; + --transition + if (count_ok = '1') then + step_sig <= '1'; + instr_n <= instr_next; + else + instr_n <= instr_c; + end if; + + when Cp_search => + --signals + cp_en <= '1'; + --transition + if (cp_ok = '1') then + case instr_c.context_uut is + when "01" => + ram_1.we <= '1'; + ram_1.addr_up <= '1'; + ram_1.sel <= '1'; + when "10" => + ram_2.we <= '1'; + ram_2.addr_up <= '1'; + ram_2.sel <= '1'; + when others => + end case; + instr_n <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded + else + instr_n <= instr_c; + end if; + + when Cp_save => + --signals + cp_en <= '1'; + case instr_c.context_uut is + when "01" => + ram_1.we <= '1'; + ram_1.addr_up <= '1'; + ram_1.sel <= '1'; + when "10" => + ram_2.we <= '1'; + ram_2.addr_up <= '1'; + ram_2.sel <= '1'; + when others => + end case; + --transition + if (cp_ok = '0') then + case instr_c.context_uut is + when "01" => + ram_1.we <= '0'; + ram_1.addr_up <= '0'; + when "10" => + ram_2.we <= '0'; + ram_2.addr_up <= '0'; + when others => + end case; + step_sig <= '1'; + instr_n <= instr_next; + else + instr_n <= instr_c; + end if; + + when Idle => + --signals + count_max <= instr_c.arg; + count_en <= '1'; + --transition + if (count_ok = '1') then + step_sig <= '1'; + instr_n <= instr_next; + else + instr_n <= instr_c; + end if; + + when Rst_uut => + --signals + reset_fsm <= '1'; + ram_1.addr_z <= '1'; + ram_2.addr_z <= '1'; + --transition + step_sig <= '1'; + instr_n <= instr_next; + + when Rest_ini0 => + --signals + start <= '1'; + cp_en <= '1'; + cp_rest <= '1'; + --this is for restoration : reading the first word of the right memory + case instr_c.context_uut is + when "01" => + ram_1.sel <= '1'; + when "10" => + ram_2.sel <= '1'; + when others => + end case; + --transition + instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded + + when Rest_ini1 => + --signals + cp_en <= '1'; + cp_rest <= '1'; + case instr_c.context_uut is + when "01" => + ram_1.addr_up <= '1'; + ram_1.sel <= '1'; + when "10" => + ram_2.addr_up <= '1'; + ram_2.sel <= '1'; + when others => + end case; + --transition + instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded + + when Rest => + --signals + cp_en <= '1'; + cp_rest <= '1'; + case instr_c.context_uut is + when "01" => + ram_1.addr_up <= '1'; + ram_1.sel <= '1'; + when "10" => + ram_2.addr_up <= '1'; + ram_2.sel <= '1'; + when others => + end case; + --transition + if (cp_ok = '0') then + step_sig <= '1'; + instr_n <= instr_next; + else + instr_n <= instr_c; + end if; + + when Stop => + --signals + stopped <= '1'; + reset_fsm <= '1'; + report "RUNTIME:" & integer'image(runtime); + assert (vecs_found = '0') + report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note; + --transition + instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded + + when others => + end case; + end process comb_logic; + + --*ER reset combo logic + --if a step_sig signal is sent, it means a instr_next will be consumed + reseter : process(step_sig) + begin + if (step_sig = '0') then + times_z <= '0'; + count_z <= '0'; + else + times_z <= '1'; + count_z <= '1'; + end if; + end process reseter; + + --TIMER + timer : process(clock, reset) + begin + if (reset = '1') then + times <= (others => '0'); + times_ok <= '0'; + elsif rising_edge(clock) then + if (times_z = '1') then + times <= (others => '0'); + times_ok <= '0'; + else + if (times_en = '1') then + times <= times + 1; + if (times = times_max) then + times_ok <= '1'; + else + times_ok <= '0'; + end if; + end if; + end if; + end if; + end process timer; + + --COUNTER + counter : process(clock, reset) + begin + if (reset = '1') then + count <= (others => '0'); + count_ok <= '0'; + elsif rising_edge(clock) then + --count_ok driving if + if (count_z = '1') then + count_ok <= '0'; + count <= (others => '0'); + else + if (count = count_max) then + count_ok <= '1'; + else + count_ok <= '0'; + if (count_en = '1') then + count <= count + 1; + end if; + end if; + end if; + end if; + end process counter; + + --Runtime counter + runtime_counter : process(clock, reset) + begin + if (reset = '1') then + runtime <= 0; + elsif rising_edge(clock) then + if (runtime_en = '1') then + runtime <= runtime + 1; + if ((runtime mod 1000) = 0) then + report "Running since:" & integer'image(runtime) severity note; + end if; + end if; + end if; + end process runtime_counter; + + -- process only used for reporting current instruction + reporter : process(instr_c) + begin + --report "Instruction: " & state_t'image(instr_c.state) severity note; + report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note; + end process reporter; + + --Combinational + step <= step_sig; + context_uut <= instr_c.context_uut; +end rtl; diff --git a/testsuite/gna/issue50/vector.d/fsm_15.vhd b/testsuite/gna/issue50/vector.d/fsm_15.vhd new file mode 100644 index 000000000..576089e8b --- /dev/null +++ b/testsuite/gna/issue50/vector.d/fsm_15.vhd @@ -0,0 +1,539 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity fsm_15 is + port ( + clock : in std_logic; + reset : in std_logic; + out3 : out std_logic; + out157 : out std_logic; + out159 : out std_logic; + out160 : out std_logic; + out171 : out std_logic; + out172 : out std_logic; + out173 : out std_logic; + out175 : out std_logic; + out178 : out std_logic; + in0 : in std_logic; + out0 : out std_logic; + in5 : in std_logic; + in6 : in std_logic; + in7 : in std_logic; + out35 : out std_logic; + out39 : out std_logic; + out40 : out std_logic; + out41 : out std_logic; + out44 : out std_logic; + out46 : out std_logic; + out140 : out std_logic; + in8 : in std_logic; + in9 : in std_logic; + in10 : in std_logic; + in11 : in std_logic; + in12 : in std_logic; + in13 : in std_logic; + in14 : in std_logic; + out65 : out std_logic; + in1 : in std_logic; + in2 : in std_logic; + in3 : in std_logic; + in4 : in std_logic; + out225 : out std_logic; + out227 : out std_logic; + out231 : out std_logic; + out235 : out std_logic; + out236 : out std_logic; + out237 : out std_logic; + out238 : out std_logic; + out97 : out std_logic; + out98 : out std_logic; + out101 : out std_logic; + out102 : out std_logic; + out124 : out std_logic; + out125 : out std_logic; + out80 : out std_logic; + out81 : out std_logic; + out84 : out std_logic; + out86 : out std_logic; + out88 : out std_logic; + out93 : out std_logic; + out94 : out std_logic + ); +end fsm_15; + +architecture augh of fsm_15 is + + signal state_cur : std_logic_vector(0 to 21) := (19 => '1', others => '0'); + signal state_next : std_logic_vector(0 to 21) := (19 => '1', others => '0'); + + -- Buffers for outputs + signal out0_buf : std_logic := '0'; + signal out0_bufn : std_logic; + signal out40_buf : std_logic := '0'; + signal out40_bufn : std_logic; + signal out101_buf : std_logic := '0'; + signal out101_bufn : std_logic; + signal out172_buf : std_logic := '0'; + signal out172_bufn : std_logic; + + -- Function calls: return IDs + signal funccall0 : unsigned(0 downto 0) := (others => '0'); + signal funccall0_next : unsigned(0 downto 0) := (others => '0'); + +begin + + -- Sequential process + -- Set the current state + + process (clock) + begin + if rising_edge(clock) then + + -- Next state + state_cur <= state_next; + -- Buffers for outputs + out0_buf <= out0_bufn; + out40_buf <= out40_bufn; + out101_buf <= out101_bufn; + out172_buf <= out172_bufn; + -- Function calls: return IDs + funccall0 <= funccall0_next; + + end if; + end process; + + -- Combinatorial process + -- Compute the next state + -- Compute the outputs + + process ( + -- Inputs of the FSM + reset, in0, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in1, in2, in3, in4, + -- Function calls: return IDs + funccall0, + -- Current state + state_cur + ) + begin + + -- Reset the next state value + + state_next <= (others => '0'); + + -- Default value to the outputs or output buffers + + out46 <= '0'; + out35 <= '0'; + out65 <= '0'; + out39 <= '0'; + out3 <= '0'; + out44 <= '0'; + out0_bufn <= '0'; + out41 <= '0'; + out40_bufn <= '0'; + out80 <= '0'; + out81 <= '0'; + out84 <= '0'; + out86 <= '0'; + out88 <= '0'; + out93 <= '0'; + out94 <= '0'; + out97 <= '0'; + out98 <= '0'; + out101_bufn <= '0'; + out102 <= '0'; + out124 <= '0'; + out125 <= '0'; + out140 <= '0'; + out157 <= '0'; + out159 <= '0'; + out160 <= '0'; + out171 <= '0'; + out172_bufn <= '0'; + out173 <= '0'; + out175 <= '0'; + out178 <= '0'; + out225 <= '0'; + out227 <= '0'; + out231 <= '0'; + out235 <= '0'; + out236 <= '0'; + out237 <= '0'; + out238 <= '0'; + + -- Function calls: default values (no change) + funccall0_next <= funccall0; + + -- For all states, compute the next state bits + -- And the outputs, and the next value for buffered outputs + + if state_cur(0) = '1' then + -- Next state + if ((in4) or (in3) or (in2)) = '1' then + state_next(17) <= '1'; + -- Next values for buffered outputs + else + if (in1) = '1' then + -- Function call: memextrct_0 + -- Save the origin of the call + funccall0_next <= to_unsigned(0, 1); + -- This is where the function call leads + state_next(4) <= '1'; + -- Next values for buffered outputs + out0_bufn <= '1'; + else + if (in0) = '1' then + -- Function call: memextrct_1 + state_next(2) <= '1'; + -- Next values for buffered outputs + out0_bufn <= '1'; + else + state_next(17) <= '1'; + -- Next values for buffered outputs + end if; + end if; + end if; + -- Assignment of non-buffered outputs + out3 <= '1'; + end if; + + if state_cur(1) = '1' then + -- Next state + if (in5) = '1' then + state_next(1) <= '1'; + -- Next values for buffered outputs + out40_bufn <= '1'; + else + -- Return from function: memextrct_1 + -- Function call: memextrct_0 + -- Save the origin of the call + funccall0_next <= to_unsigned(1, 1); + -- This is where the function call leads + state_next(4) <= '1'; + -- Next values for buffered outputs + out0_bufn <= '1'; + end if; + -- Assignment of non-buffered outputs + out41 <= '1'; + out39 <= '1'; + out35 <= '1'; + end if; + + if state_cur(2) = '1' then + -- Next state + state_next(1) <= '1'; + -- Next values for buffered outputs + out40_bufn <= '1'; + -- Assignment of non-buffered outputs + out44 <= '1'; + end if; + + if state_cur(3) = '1' then + -- Next state + if (in6) = '1' then + state_next(3) <= '1'; + -- Next values for buffered outputs + out40_bufn <= '1'; + else + -- Return from function: memextrct_0 + if funccall0 = 1 then + state_next(17) <= '1'; + -- Next values for buffered outputs + end if; + -- Return from function: memextrct_0 + if funccall0 = 0 then + state_next(17) <= '1'; + -- Next values for buffered outputs + end if; + end if; + -- Assignment of non-buffered outputs + out41 <= '1'; + out65 <= '1'; + out46 <= '1'; + end if; + + if state_cur(4) = '1' then + -- Next state + state_next(3) <= '1'; + -- Next values for buffered outputs + out40_bufn <= '1'; + -- Assignment of non-buffered outputs + out44 <= '1'; + end if; + + if state_cur(5) = '1' then + -- Next state + if (in8) = '1' then + state_next(20) <= '1'; + -- Next values for buffered outputs + else + if (not (in7)) = '1' then + state_next(5) <= '1'; + -- Next values for buffered outputs + else + state_next(6) <= '1'; + -- Next values for buffered outputs + end if; + end if; + -- Assignment of non-buffered outputs + out84 <= '1'; + out81 <= '1'; + out80 <= '1'; + end if; + + if state_cur(6) = '1' then + -- Next state + if (in8) = '1' then + state_next(20) <= '1'; + -- Next values for buffered outputs + else + if (not (in9)) = '1' then + state_next(6) <= '1'; + -- Next values for buffered outputs + else + state_next(7) <= '1'; + -- Next values for buffered outputs + end if; + end if; + -- Assignment of non-buffered outputs + out88 <= '1'; + out86 <= '1'; + out81 <= '1'; + end if; + + if state_cur(7) = '1' then + -- Next state + if (in8) = '1' then + state_next(20) <= '1'; + -- Next values for buffered outputs + else + if (not (in9)) = '1' then + state_next(7) <= '1'; + -- Next values for buffered outputs + else + state_next(16) <= '1'; + -- Next values for buffered outputs + end if; + end if; + -- Assignment of non-buffered outputs + out94 <= '1'; + out93 <= '1'; + out81 <= '1'; + end if; + + if state_cur(8) = '1' then + -- Next state + state_next(14) <= '1'; + -- Next values for buffered outputs + -- Assignment of non-buffered outputs + out98 <= '1'; + out97 <= '1'; + end if; + + if state_cur(9) = '1' then + -- Next state + if (in10) = '1' then + state_next(10) <= '1'; + -- Next values for buffered outputs + out101_bufn <= '1'; + else + state_next(5) <= '1'; + -- Next values for buffered outputs + end if; + -- Assignment of non-buffered outputs + end if; + + if state_cur(10) = '1' then + -- Next state + state_next(11) <= '1'; + -- Next values for buffered outputs + -- Assignment of non-buffered outputs + out102 <= '1'; + end if; + + if state_cur(11) = '1' then + -- Next state + state_next(13) <= '1'; + -- Next values for buffered outputs + out172_bufn <= '1'; + -- Assignment of non-buffered outputs + out125 <= '1'; + out124 <= '1'; + end if; + + if state_cur(12) = '1' then + -- Next state + state_next(9) <= '1'; + -- Next values for buffered outputs + -- Assignment of non-buffered outputs + out159 <= '1'; + out157 <= '1'; + out140 <= '1'; + end if; + + if state_cur(13) = '1' then + -- Next state + if (in8) = '1' then + state_next(20) <= '1'; + -- Next values for buffered outputs + else + state_next(9) <= '1'; + -- Next values for buffered outputs + end if; + -- Assignment of non-buffered outputs + out173 <= '1'; + out171 <= '1'; + out160 <= '1'; + out81 <= '1'; + end if; + + if state_cur(14) = '1' then + -- Next state + if (in11) = '1' then + state_next(15) <= '1'; + -- Next values for buffered outputs + out172_bufn <= '1'; + out101_bufn <= '1'; + else + state_next(12) <= '1'; + -- Next values for buffered outputs + end if; + -- Assignment of non-buffered outputs + end if; + + if state_cur(15) = '1' then + -- Next state + if (in8) = '1' then + state_next(20) <= '1'; + -- Next values for buffered outputs + else + state_next(14) <= '1'; + -- Next values for buffered outputs + end if; + -- Assignment of non-buffered outputs + out173 <= '1'; + out178 <= '1'; + out175 <= '1'; + out81 <= '1'; + end if; + + if state_cur(16) = '1' then + -- Next state + state_next(8) <= '1'; + -- Next values for buffered outputs + -- Assignment of non-buffered outputs + out159 <= '1'; + out227 <= '1'; + out225 <= '1'; + end if; + + if state_cur(17) = '1' then + -- Next state + if (in12) = '1' then + if (in4) = '1' then + state_next(5) <= '1'; + -- Next values for buffered outputs + else + if (in3) = '1' then + state_next(6) <= '1'; + -- Next values for buffered outputs + else + if (in2) = '1' then + state_next(7) <= '1'; + -- Next values for buffered outputs + else + if (in1) = '1' then + state_next(13) <= '1'; + -- Next values for buffered outputs + out172_bufn <= '1'; + else + state_next(15) <= '1'; + -- Next values for buffered outputs + out172_bufn <= '1'; + out101_bufn <= '1'; + end if; + end if; + end if; + end if; + else + state_next(18) <= '1'; + -- Next values for buffered outputs + end if; + -- Assignment of non-buffered outputs + out231 <= '1'; + end if; + + if state_cur(18) = '1' then + -- Next state + state_next(18) <= '1'; + -- Next values for buffered outputs + -- Assignment of non-buffered outputs + end if; + + -- Info: This is the init/reset state + if state_cur(19) = '1' then + -- Next state + if (not (in13)) = '1' then + state_next(19) <= '1'; + -- Next values for buffered outputs + else + if (in12) = '1' then + state_next(20) <= '1'; + -- Next values for buffered outputs + else + state_next(6) <= '1'; + -- Next values for buffered outputs + end if; + end if; + -- Assignment of non-buffered outputs + out236 <= '1'; + out235 <= '1'; + end if; + + if state_cur(20) = '1' then + -- Next state + state_next(21) <= '1'; + -- Next values for buffered outputs + -- Assignment of non-buffered outputs + out44 <= '1'; + end if; + + if state_cur(21) = '1' then + -- Next state + if (in14) = '1' then + state_next(21) <= '1'; + -- Next values for buffered outputs + else + state_next(0) <= '1'; + -- Next values for buffered outputs + out0_bufn <= '1'; + end if; + -- Assignment of non-buffered outputs + out41 <= '1'; + out238 <= '1'; + out237 <= '1'; + end if; + + -- Reset input + if reset = '1' then + -- Set the reset state + state_next <= (19 => '1', others => '0'); + -- Note: Resetting all buffers for outputs here is not necessary. + -- It would cost hardware. They will be reset at the next clock front. + -- Reset state: set the buffered outputs + end if; + + end process; + + -- Assignment of buffered outputs + + out0 <= out0_buf; + out40 <= out40_buf; + out101 <= out101_buf; + out172 <= out172_buf; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/muxb_117.vhd b/testsuite/gna/issue50/vector.d/muxb_117.vhd new file mode 100644 index 000000000..6f615b120 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/muxb_117.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_117 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); +end muxb_117; + +architecture augh of muxb_117 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/muxb_120.vhd b/testsuite/gna/issue50/vector.d/muxb_120.vhd new file mode 100644 index 000000000..e04495904 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/muxb_120.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_120 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); +end muxb_120; + +architecture augh of muxb_120 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/muxb_121.vhd b/testsuite/gna/issue50/vector.d/muxb_121.vhd new file mode 100644 index 000000000..a87b25e2e --- /dev/null +++ b/testsuite/gna/issue50/vector.d/muxb_121.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_121 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); +end muxb_121; + +architecture augh of muxb_121 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/muxb_123.vhd b/testsuite/gna/issue50/vector.d/muxb_123.vhd new file mode 100644 index 000000000..150ed33cd --- /dev/null +++ b/testsuite/gna/issue50/vector.d/muxb_123.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_123 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); +end muxb_123; + +architecture augh of muxb_123 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/muxb_124.vhd b/testsuite/gna/issue50/vector.d/muxb_124.vhd new file mode 100644 index 000000000..72f4f37dc --- /dev/null +++ b/testsuite/gna/issue50/vector.d/muxb_124.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_124 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); +end muxb_124; + +architecture augh of muxb_124 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/muxb_219.vhd b/testsuite/gna/issue50/vector.d/muxb_219.vhd new file mode 100644 index 000000000..d26913c7c --- /dev/null +++ b/testsuite/gna/issue50/vector.d/muxb_219.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_219 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); +end muxb_219; + +architecture augh of muxb_219 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/issue50/vector.d/pkg_tb.vhd b/testsuite/gna/issue50/vector.d/pkg_tb.vhd new file mode 100644 index 000000000..89886725d --- /dev/null +++ b/testsuite/gna/issue50/vector.d/pkg_tb.vhd @@ -0,0 +1,60 @@ +--test bench written by alban bourge @ tima +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pkg_tb is + + --fsm state types + type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop); + --context descriptor + subtype context_t is std_logic_vector(1 downto 0); + --argument width and type of fsm instruction + constant ARG_WIDTH : integer := 8; + subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0); + + type instruction is + record + state : state_t; + context_uut : context_t; + arg : argument_t; + end record; + + --reset instruction + constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0')); + + --ram instruction + type ram_instruction is + record + sel : std_logic; + we : std_logic; + addr_up : std_logic; + addr_z : std_logic; + end record; + + constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0'); + + --assert unit instruction + type assert_instruction is + record + en_feed : std_logic; + en_check : std_logic; + end record; + + constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0'); + + --size of instruction table defined by PC_SIZE i.e. width of program counter + constant PC_SIZE : integer := 5; + type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction; + + --constraint fixed by unit under test (augh dependant) + --##CONSTRAINTS_START##-- + subtype stdin_vector is std_logic_vector(31 downto 0); + subtype stdout_vector is std_logic_vector(31 downto 0); + subtype cp_vector is std_logic_vector(63 downto 0); + --##CONSTRAINTS_END##-- + + --assert_uut vector number counter size + constant VEC_NO_SIZE : integer := 20; + +end pkg_tb; diff --git a/testsuite/gna/issue50/vector.d/prog.vhd b/testsuite/gna/issue50/vector.d/prog.vhd new file mode 100644 index 000000000..4d7aa42db --- /dev/null +++ b/testsuite/gna/issue50/vector.d/prog.vhd @@ -0,0 +1,71 @@ +--test bench written by Alban Bourge @ TIMA +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkg_tb.all; + +entity prog is + port( + clock : in std_logic; + reset : in std_logic; + step : in std_logic; + instr_next : out instruction + ); +end prog; + +architecture rtl of prog is + + signal instr_n : instruction := instr_rst; + + --Table describing fsm behavior + constant fsm_behavior : table_behavior := ( + --##PROGRAM_GOES_DOWN_HERE##-- + 0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), + 1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), + 2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)), + 3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(2,ARG_WIDTH)), + 4 => (state => Running, context_uut => "01", arg => to_unsigned(5,ARG_WIDTH)), + 5 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)), + 6 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), + 7 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), + 8 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), + 9 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)), + 10 => (state => Ack_data, context_uut => "10", arg => to_unsigned(2,ARG_WIDTH)), + 11 => (state => Running, context_uut => "10", arg => to_unsigned(6,ARG_WIDTH)), + 12 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)), + 13 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), + 14 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), + 15 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), + 16 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)), + 17 => (state => Waitfor, context_uut => "01", arg => to_unsigned(1,ARG_WIDTH)), + 18 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), + 19 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), + 20 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), + 21 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)), + 22 => (state => Waitfor, context_uut => "10", arg => to_unsigned(1,ARG_WIDTH)), + 23 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), + --##PROGRAM_GOES_OVER_HERE##-- + others => instr_rst); + + signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0'); + +begin + + drive_state : process (reset,clock) is + begin + if reset = '1' then + instr_n <= instr_rst; + pc <= (others => '0'); + elsif rising_edge(clock) then + if (step = '1') then + pc <= pc + 1; + end if; + instr_n <= fsm_behavior(to_integer(pc)); + end if; + end process drive_state; + + --instr_next <= instr_n; + instr_next <= fsm_behavior(to_integer(pc)); + +end rtl; diff --git a/testsuite/gna/issue50/vector.d/sub_125.vhd b/testsuite/gna/issue50/vector.d/sub_125.vhd new file mode 100644 index 000000000..dd458f161 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/sub_125.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_125 is + port ( + le : out std_logic; + sign : in std_logic; + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); +end sub_125; + +architecture augh of sub_125 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(32 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + le <= tmp_le; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/sub_145.vhd b/testsuite/gna/issue50/vector.d/sub_145.vhd new file mode 100644 index 000000000..d8fe56a80 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/sub_145.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_145 is + port ( + result : out std_logic_vector(3 downto 0); + in_a : in std_logic_vector(3 downto 0); + in_b : in std_logic_vector(3 downto 0) + ); +end sub_145; + +architecture augh of sub_145 is + + signal carry_inA : std_logic_vector(5 downto 0); + signal carry_inB : std_logic_vector(5 downto 0); + signal carry_res : std_logic_vector(5 downto 0); + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(4 downto 1); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/sub_189.vhd b/testsuite/gna/issue50/vector.d/sub_189.vhd new file mode 100644 index 000000000..02a52c0d2 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/sub_189.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_189 is + port ( + lt : out std_logic; + sign : in std_logic; + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); +end sub_189; + +architecture augh of sub_189 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(32 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + lt <= not(tmp_ge); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/sync_ram.vhd b/testsuite/gna/issue50/vector.d/sync_ram.vhd new file mode 100644 index 000000000..83aecf543 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/sync_ram.vhd @@ -0,0 +1,42 @@ +-- Simple generic RAM Model +-- +-- +-----------------------------+ +-- | Copyright 2008 DOULOS | +-- | designer : JK | +-- +-----------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sync_ram is + port ( + clock : in std_logic; + we : in std_logic; + address : in std_logic_vector; + datain : in std_logic_vector; + dataout : out std_logic_vector + ); +end entity sync_ram; + +architecture rtl of sync_ram is + + type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range); + signal ram : ram_type; + signal read_address : std_logic_vector(address'range); + +begin + + ramproc: process(clock) is + begin + if rising_edge(clock) then + if we = '1' then + ram(to_integer(unsigned(address))) <= datain; + end if; + read_address <= address; + end if; + end process ramproc; + + dataout <= ram(to_integer(unsigned(read_address))); + +end architecture rtl; diff --git a/testsuite/gna/issue50/vector.d/tb.vhd b/testsuite/gna/issue50/vector.d/tb.vhd new file mode 100644 index 000000000..94a534963 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/tb.vhd @@ -0,0 +1,44 @@ +--test bench written by Alban Bourge @ TIMA +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkg_tb.all; + +entity tb is +end tb; + +architecture behavior of tb is + + signal clock : std_logic := '0'; + signal clock_next : std_logic := '0'; + signal reset : std_logic := '0'; + --TOP signals + signal n_error : std_logic; + signal stopped : std_logic; + +begin + + test : entity work.cp3_test(rtl) + port map( + clock => clock, + reset => reset, + n_error => n_error, + stopped => stopped + ); + + --clock generator + clock <= clock_next after 10 ns; + clock_next <= not clock when stopped = '0' else '0'; + + reset_proc : process + begin + reset <= '1'; + for i in 1 to 5 loop + wait until rising_edge(clock); + end loop; + reset <= '0'; + wait; + end process reset_proc; + +end behavior; diff --git a/testsuite/gna/issue50/vector.d/top.vhd b/testsuite/gna/issue50/vector.d/top.vhd new file mode 100644 index 000000000..b82be5e72 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/top.vhd @@ -0,0 +1,2504 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clock : in std_logic; + reset : in std_logic; + start : in std_logic; + stdin_data : in std_logic_vector(31 downto 0); + stdin_rdy : out std_logic; + stdin_ack : in std_logic; + stdout_data : out std_logic_vector(31 downto 0); + stdout_rdy : out std_logic; + stdout_ack : in std_logic; + cp_en : in std_logic; + cp_rest : in std_logic; + cp_din : in std_logic_vector(63 downto 0); + cp_dout : out std_logic_vector(63 downto 0); + cp_ok : out std_logic + ); +end top; + +architecture augh of top is + + -- Declaration of components + + component v_split0 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split1 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split2 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split3 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split4 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split5 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split6 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component v_split7 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split0 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split1 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split2 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split3 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split4 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split5 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split6 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component w_split7 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); + end component; + + component add_171 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_183 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_185 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_193 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_195 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component muxb_120 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); + end component; + + component muxb_124 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); + end component; + + component cmp_128 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_130 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_132 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_136 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_137 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_138 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_139 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_140 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_141 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_142 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component muxb_117 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); + end component; + + component add_118 is + port ( + result : out std_logic_vector(15 downto 0); + in_a : in std_logic_vector(15 downto 0); + in_b : in std_logic_vector(15 downto 0) + ); + end component; + + component cmp_119 is + port ( + ne : out std_logic; + in0 : in std_logic_vector(15 downto 0); + in1 : in std_logic_vector(15 downto 0) + ); + end component; + + component muxb_121 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); + end component; + + component muxb_123 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); + end component; + + component sub_125 is + port ( + le : out std_logic; + sign : in std_logic; + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_126 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component add_134 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); + end component; + + component sub_145 is + port ( + result : out std_logic_vector(3 downto 0); + in_a : in std_logic_vector(3 downto 0); + in_b : in std_logic_vector(3 downto 0) + ); + end component; + + component cmp_146 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component add_170 is + port ( + result : out std_logic_vector(8 downto 0); + in_a : in std_logic_vector(8 downto 0); + in_b : in std_logic_vector(8 downto 0) + ); + end component; + + component cmp_174 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_176 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_178 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_180 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_187 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component add_188 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); + end component; + + component sub_189 is + port ( + lt : out std_logic; + sign : in std_logic; + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_191 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_198 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_200 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_202 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_204 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component add_214 is + port ( + result : out std_logic_vector(7 downto 0); + in_a : in std_logic_vector(7 downto 0); + in_b : in std_logic_vector(7 downto 0) + ); + end component; + + component cmp_215 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component muxb_219 is + port ( + in_sel : in std_logic; + out_data : out std_logic; + in_data0 : in std_logic; + in_data1 : in std_logic + ); + end component; + + component add_220 is + port ( + result : out std_logic_vector(15 downto 0); + in_a : in std_logic_vector(15 downto 0); + in_b : in std_logic_vector(15 downto 0) + ); + end component; + + component cmp_221 is + port ( + ne : out std_logic; + in0 : in std_logic_vector(15 downto 0); + in1 : in std_logic_vector(15 downto 0) + ); + end component; + + component cmp_111 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_113 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_216 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_217 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_218 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component fsm_15 is + port ( + clock : in std_logic; + reset : in std_logic; + out3 : out std_logic; + out157 : out std_logic; + out159 : out std_logic; + out160 : out std_logic; + out171 : out std_logic; + out172 : out std_logic; + out173 : out std_logic; + out175 : out std_logic; + out178 : out std_logic; + in0 : in std_logic; + out0 : out std_logic; + in5 : in std_logic; + in6 : in std_logic; + in7 : in std_logic; + out35 : out std_logic; + out39 : out std_logic; + out40 : out std_logic; + out41 : out std_logic; + out44 : out std_logic; + out46 : out std_logic; + out140 : out std_logic; + in8 : in std_logic; + in9 : in std_logic; + in10 : in std_logic; + in11 : in std_logic; + in12 : in std_logic; + in13 : in std_logic; + in14 : in std_logic; + out65 : out std_logic; + in1 : in std_logic; + in2 : in std_logic; + in3 : in std_logic; + in4 : in std_logic; + out225 : out std_logic; + out227 : out std_logic; + out231 : out std_logic; + out235 : out std_logic; + out236 : out std_logic; + out237 : out std_logic; + out238 : out std_logic; + out97 : out std_logic; + out98 : out std_logic; + out101 : out std_logic; + out102 : out std_logic; + out124 : out std_logic; + out125 : out std_logic; + out80 : out std_logic; + out81 : out std_logic; + out84 : out std_logic; + out86 : out std_logic; + out88 : out std_logic; + out93 : out std_logic; + out94 : out std_logic + ); + end component; + + component cmp_112 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_114 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_115 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_148 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_150 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_152 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_154 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_156 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_158 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_160 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_127 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_129 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_131 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_133 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_135 is + port ( + eq : out std_logic; + in0 : in std_logic_vector(2 downto 0); + in1 : in std_logic_vector(2 downto 0) + ); + end component; + + -- Declaration of signals + + signal sig_clock : std_logic; + signal sig_reset : std_logic; + signal sig_222 : std_logic; + signal sig_223 : std_logic; + signal sig_224 : std_logic; + signal sig_225 : std_logic; + signal sig_226 : std_logic; + signal sig_227 : std_logic; + signal sig_228 : std_logic; + signal sig_229 : std_logic; + signal sig_230 : std_logic; + signal sig_231 : std_logic; + signal sig_232 : std_logic; + signal sig_233 : std_logic; + signal sig_234 : std_logic; + signal sig_235 : std_logic; + signal sig_236 : std_logic; + signal sig_237 : std_logic; + signal sig_238 : std_logic; + signal sig_239 : std_logic; + signal sig_240 : std_logic; + signal sig_241 : std_logic; + signal sig_242 : std_logic; + signal sig_243 : std_logic; + signal sig_244 : std_logic; + signal sig_245 : std_logic; + signal sig_246 : std_logic; + signal sig_247 : std_logic; + signal sig_248 : std_logic; + signal sig_249 : std_logic; + signal sig_250 : std_logic; + signal sig_251 : std_logic; + signal sig_252 : std_logic; + signal sig_253 : std_logic; + signal sig_254 : std_logic; + signal sig_255 : std_logic; + signal sig_256 : std_logic; + signal sig_257 : std_logic; + signal sig_258 : std_logic; + signal sig_259 : std_logic; + signal sig_260 : std_logic; + signal sig_261 : std_logic; + signal sig_262 : std_logic; + signal sig_263 : std_logic; + signal sig_264 : std_logic; + signal sig_265 : std_logic; + signal sig_266 : std_logic; + signal sig_267 : std_logic; + signal sig_268 : std_logic; + signal sig_269 : std_logic; + signal sig_270 : std_logic; + signal sig_271 : std_logic; + signal sig_272 : std_logic; + signal sig_273 : std_logic; + signal sig_274 : std_logic; + signal sig_275 : std_logic; + signal sig_276 : std_logic; + signal sig_277 : std_logic; + signal sig_278 : std_logic; + signal augh_test_0 : std_logic; + signal augh_test_1 : std_logic; + signal sig_start : std_logic; + signal test_cp_4_6 : std_logic; + signal test_cp_3_7 : std_logic; + signal test_cp_0_8 : std_logic; + signal test_cp_1_9 : std_logic; + signal test_cp_2_10 : std_logic; + signal memextrct_loop_sig_13 : std_logic; + signal memextrct_loop_sig_14 : std_logic; + signal psc_loop_sig_12 : std_logic; + signal sig_279 : std_logic_vector(15 downto 0); + signal sig_280 : std_logic; + signal sig_281 : std_logic; + signal sig_282 : std_logic_vector(7 downto 0); + signal sig_283 : std_logic; + signal sig_284 : std_logic; + signal sig_285 : std_logic; + signal sig_286 : std_logic; + signal sig_287 : std_logic; + signal sig_288 : std_logic_vector(31 downto 0); + signal sig_289 : std_logic_vector(31 downto 0); + signal sig_290 : std_logic; + signal sig_291 : std_logic; + signal sig_292 : std_logic; + signal sig_293 : std_logic; + signal sig_294 : std_logic; + signal sig_295 : std_logic_vector(8 downto 0); + signal sig_296 : std_logic; + signal sig_297 : std_logic_vector(3 downto 0); + signal sig_298 : std_logic_vector(31 downto 0); + signal sig_299 : std_logic; + signal sig_300 : std_logic_vector(31 downto 0); + signal sig_301 : std_logic; + signal sig_302 : std_logic; + signal sig_303 : std_logic; + signal sig_304 : std_logic_vector(15 downto 0); + signal sig_305 : std_logic; + signal sig_306 : std_logic; + signal sig_307 : std_logic; + signal sig_308 : std_logic; + signal sig_309 : std_logic; + signal sig_310 : std_logic; + signal sig_311 : std_logic; + signal sig_312 : std_logic; + signal sig_313 : std_logic; + signal sig_314 : std_logic; + signal sig_315 : std_logic; + signal sig_316 : std_logic; + signal sig_317 : std_logic; + signal sig_318 : std_logic; + signal sig_319 : std_logic; + signal sig_320 : std_logic; + signal sig_321 : std_logic; + signal sig_322 : std_logic_vector(31 downto 0); + signal sig_323 : std_logic_vector(7 downto 0); + signal sig_324 : std_logic_vector(7 downto 0); + signal sig_325 : std_logic_vector(7 downto 0); + signal sig_326 : std_logic_vector(7 downto 0); + signal sig_327 : std_logic_vector(7 downto 0); + signal sig_328 : std_logic_vector(7 downto 0); + signal sig_329 : std_logic_vector(7 downto 0); + signal sig_330 : std_logic_vector(7 downto 0); + signal sig_331 : std_logic_vector(7 downto 0); + signal sig_332 : std_logic_vector(7 downto 0); + signal sig_333 : std_logic_vector(7 downto 0); + signal sig_334 : std_logic_vector(7 downto 0); + signal sig_335 : std_logic_vector(7 downto 0); + signal sig_336 : std_logic_vector(7 downto 0); + signal sig_337 : std_logic_vector(7 downto 0); + signal sig_338 : std_logic_vector(7 downto 0); + signal sig_339 : std_logic_vector(31 downto 0); + signal sig_340 : std_logic_vector(8 downto 0); + signal sig_341 : std_logic_vector(8 downto 0); + signal sig_342 : std_logic_vector(31 downto 0); + + -- Other inlined components + + signal mux_25 : std_logic; + signal mux_26 : std_logic_vector(2 downto 0); + signal mux_27 : std_logic; + signal mux_28 : std_logic_vector(2 downto 0); + signal mux_29 : std_logic; + signal mux_30 : std_logic_vector(15 downto 0); + signal mux_31 : std_logic; + signal mux_32 : std_logic_vector(7 downto 0); + signal mux_33 : std_logic; + signal mux_34 : std_logic; + signal mux_35 : std_logic; + signal mux_36 : std_logic_vector(7 downto 0); + signal mux_37 : std_logic; + signal mux_38 : std_logic; + signal mux_39 : std_logic; + signal mux_40 : std_logic_vector(7 downto 0); + signal mux_41 : std_logic; + signal mux_42 : std_logic; + signal mux_43 : std_logic; + signal augh_main_max_iter : std_logic_vector(31 downto 0) := (others => '0'); + signal augh_main_std_addition : std_logic_vector(31 downto 0) := (others => '0'); + signal augh_main_result : std_logic_vector(31 downto 0) := (others => '0'); + signal augh_main_i : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_23 : std_logic; + signal mux_24 : std_logic; + signal mux_44 : std_logic_vector(7 downto 0); + signal mux_45 : std_logic; + signal mux_46 : std_logic; + signal mux_47 : std_logic; + signal mux_48 : std_logic_vector(7 downto 0); + signal mux_49 : std_logic; + signal mux_50 : std_logic; + signal mux_51 : std_logic; + signal mux_52 : std_logic_vector(7 downto 0); + signal mux_53 : std_logic; + signal mux_54 : std_logic; + signal mux_55 : std_logic; + signal mux_56 : std_logic_vector(7 downto 0); + signal mux_57 : std_logic; + signal mux_58 : std_logic; + signal mux_59 : std_logic; + signal mux_60 : std_logic_vector(7 downto 0); + signal mux_61 : std_logic; + signal mux_62 : std_logic; + signal mux_63 : std_logic; + signal mux_64 : std_logic_vector(31 downto 0); + signal mux_65 : std_logic; + signal mux_66 : std_logic_vector(31 downto 0); + signal mux_67 : std_logic; + signal mux_68 : std_logic_vector(31 downto 0); + signal mux_69 : std_logic; + signal mux_70 : std_logic_vector(31 downto 0); + signal mux_71 : std_logic; + signal mux_72 : std_logic_vector(7 downto 0); + signal mux_73 : std_logic; + signal mux_74 : std_logic; + signal mux_75 : std_logic; + signal mux_76 : std_logic_vector(7 downto 0); + signal mux_77 : std_logic; + signal mux_78 : std_logic; + signal mux_79 : std_logic; + signal mux_80 : std_logic_vector(7 downto 0); + signal mux_20 : std_logic; + signal mux_22 : std_logic; + signal and_163 : std_logic_vector(7 downto 0); + signal and_164 : std_logic_vector(7 downto 0); + signal and_165 : std_logic_vector(7 downto 0); + signal and_166 : std_logic_vector(7 downto 0); + signal and_167 : std_logic_vector(7 downto 0); + signal and_168 : std_logic_vector(7 downto 0); + signal and_169 : std_logic_vector(7 downto 0); + signal and_182 : std_logic_vector(7 downto 0); + signal and_184 : std_logic_vector(7 downto 0); + signal and_186 : std_logic_vector(7 downto 0); + signal and_192 : std_logic; + signal and_194 : std_logic; + signal and_196 : std_logic; + signal mux_81 : std_logic; + signal mux_82 : std_logic; + signal mux_83 : std_logic; + signal mux_84 : std_logic_vector(7 downto 0); + signal mux_85 : std_logic; + signal mux_86 : std_logic; + signal mux_87 : std_logic; + signal mux_88 : std_logic_vector(7 downto 0); + signal mux_89 : std_logic; + signal mux_90 : std_logic; + signal mux_91 : std_logic; + signal mux_92 : std_logic_vector(7 downto 0); + signal mux_93 : std_logic; + signal mux_94 : std_logic; + signal mux_95 : std_logic; + signal mux_96 : std_logic_vector(7 downto 0); + signal mux_97 : std_logic; + signal mux_98 : std_logic; + signal mux_99 : std_logic; + signal mux_100 : std_logic_vector(7 downto 0); + signal mux_101 : std_logic; + signal mux_102 : std_logic; + signal mux_103 : std_logic; + signal mux_106 : std_logic; + signal mux_108 : std_logic; + signal mux_109 : std_logic_vector(63 downto 0); + signal mux_110 : std_logic; + signal and_116 : std_logic; + signal not_122 : std_logic; + signal or_143 : std_logic_vector(7 downto 0); + signal and_147 : std_logic_vector(7 downto 0); + signal and_149 : std_logic_vector(7 downto 0); + signal and_151 : std_logic_vector(7 downto 0); + signal and_153 : std_logic_vector(7 downto 0); + signal and_155 : std_logic_vector(7 downto 0); + signal and_157 : std_logic_vector(7 downto 0); + signal and_159 : std_logic_vector(7 downto 0); + signal or_161 : std_logic_vector(7 downto 0); + signal and_162 : std_logic_vector(7 downto 0); + signal or_172 : std_logic_vector(7 downto 0); + signal and_173 : std_logic_vector(7 downto 0); + signal and_175 : std_logic_vector(7 downto 0); + signal and_177 : std_logic_vector(7 downto 0); + signal and_179 : std_logic_vector(7 downto 0); + signal and_181 : std_logic_vector(7 downto 0); + signal and_190 : std_logic; + signal and_197 : std_logic; + signal and_199 : std_logic; + signal and_201 : std_logic; + signal and_203 : std_logic; + signal or_205 : std_logic_vector(7 downto 0); + signal and_206 : std_logic_vector(7 downto 0); + signal and_207 : std_logic_vector(7 downto 0); + signal and_208 : std_logic_vector(7 downto 0); + signal and_209 : std_logic_vector(7 downto 0); + signal and_210 : std_logic_vector(7 downto 0); + signal and_211 : std_logic_vector(7 downto 0); + signal and_212 : std_logic_vector(7 downto 0); + signal and_213 : std_logic_vector(7 downto 0); + signal psc_loop_reg_3 : std_logic_vector(15 downto 0) := (others => '0'); + signal cp_id_reg_4 : std_logic_vector(2 downto 0) := (others => '0'); + signal cp_id_reg_stable_5 : std_logic_vector(2 downto 0) := (others => '0'); + signal psc_stuff_reg_11 : std_logic_vector(60 downto 0) := "0000000000000000000000000000000000000000000000000000000000000"; + signal and_144 : std_logic_vector(7 downto 0); + + -- This utility function is used for to generate concatenations of std_logic + + -- Little utility function to ease concatenation of an std_logic + -- and explicitely return an std_logic_vector + function repeat(N: natural; B: std_logic) return std_logic_vector is + variable result: std_logic_vector(N-1 downto 0); + begin + result := (others => B); + return result; + end; + +begin + + -- Instantiation of components + + v_split0_i : v_split0 port map ( + clk => sig_clock, + ra0_data => sig_338, + wa0_data => mux_100, + wa0_addr => mux_101, + wa0_en => mux_102, + ra0_addr => mux_103 + ); + + v_split1_i : v_split1 port map ( + clk => sig_clock, + ra0_data => sig_337, + wa0_data => mux_96, + wa0_addr => mux_97, + wa0_en => mux_98, + ra0_addr => mux_99 + ); + + v_split2_i : v_split2 port map ( + clk => sig_clock, + ra0_data => sig_336, + wa0_data => mux_92, + wa0_addr => mux_93, + wa0_en => mux_94, + ra0_addr => mux_95 + ); + + v_split3_i : v_split3 port map ( + clk => sig_clock, + ra0_data => sig_335, + wa0_data => mux_88, + wa0_addr => mux_89, + wa0_en => mux_90, + ra0_addr => mux_91 + ); + + v_split4_i : v_split4 port map ( + clk => sig_clock, + ra0_data => sig_334, + wa0_data => mux_84, + wa0_addr => mux_85, + wa0_en => mux_86, + ra0_addr => mux_87 + ); + + v_split5_i : v_split5 port map ( + clk => sig_clock, + ra0_data => sig_333, + wa0_data => mux_80, + wa0_addr => mux_81, + wa0_en => mux_82, + ra0_addr => mux_83 + ); + + v_split6_i : v_split6 port map ( + clk => sig_clock, + ra0_data => sig_332, + wa0_data => mux_76, + wa0_addr => mux_77, + wa0_en => mux_78, + ra0_addr => mux_79 + ); + + v_split7_i : v_split7 port map ( + clk => sig_clock, + ra0_data => sig_331, + wa0_data => mux_72, + wa0_addr => mux_73, + wa0_en => mux_74, + ra0_addr => mux_75 + ); + + w_split0_i : w_split0 port map ( + clk => sig_clock, + ra0_data => sig_330, + wa0_data => mux_60, + wa0_addr => mux_61, + wa0_en => mux_62, + ra0_addr => mux_63 + ); + + w_split1_i : w_split1 port map ( + clk => sig_clock, + ra0_data => sig_329, + wa0_data => mux_56, + wa0_addr => mux_57, + wa0_en => mux_58, + ra0_addr => mux_59 + ); + + w_split2_i : w_split2 port map ( + clk => sig_clock, + ra0_data => sig_328, + wa0_data => mux_52, + wa0_addr => mux_53, + wa0_en => mux_54, + ra0_addr => mux_55 + ); + + w_split3_i : w_split3 port map ( + clk => sig_clock, + ra0_data => sig_327, + wa0_data => mux_48, + wa0_addr => mux_49, + wa0_en => mux_50, + ra0_addr => mux_51 + ); + + w_split4_i : w_split4 port map ( + clk => sig_clock, + ra0_data => sig_326, + wa0_data => mux_44, + wa0_addr => mux_45, + wa0_en => mux_46, + ra0_addr => mux_47 + ); + + w_split5_i : w_split5 port map ( + clk => sig_clock, + ra0_data => sig_325, + wa0_data => mux_40, + wa0_addr => mux_41, + wa0_en => mux_42, + ra0_addr => mux_43 + ); + + w_split6_i : w_split6 port map ( + clk => sig_clock, + ra0_data => sig_324, + wa0_data => mux_36, + wa0_addr => mux_37, + wa0_en => mux_38, + ra0_addr => mux_39 + ); + + w_split7_i : w_split7 port map ( + clk => sig_clock, + ra0_data => sig_323, + wa0_data => mux_32, + wa0_addr => mux_33, + wa0_en => mux_34, + ra0_addr => mux_35 + ); + + add_171_i : add_171 port map ( + result => sig_322, + in_a => sig_342, + in_b => augh_main_std_addition + ); + + cmp_183_i : cmp_183 port map ( + eq => sig_321, + in0 => "010", + in1 => augh_main_i(2 downto 0) + ); + + cmp_185_i : cmp_185 port map ( + eq => sig_320, + in0 => "001", + in1 => augh_main_i(2 downto 0) + ); + + cmp_193_i : cmp_193 port map ( + eq => sig_319, + in0 => "110", + in1 => augh_main_i(2 downto 0) + ); + + cmp_195_i : cmp_195 port map ( + eq => sig_318, + in0 => "101", + in1 => augh_main_i(2 downto 0) + ); + + muxb_120_i : muxb_120 port map ( + in_sel => cp_en, + out_data => sig_317, + in_data0 => '0', + in_data1 => '1' + ); + + muxb_124_i : muxb_124 port map ( + in_sel => not_122, + out_data => sig_316, + in_data0 => '0', + in_data1 => '1' + ); + + cmp_128_i : cmp_128 port map ( + eq => sig_315, + in0 => "101", + in1 => augh_main_i(2 downto 0) + ); + + cmp_130_i : cmp_130 port map ( + eq => sig_314, + in0 => "011", + in1 => augh_main_i(2 downto 0) + ); + + cmp_132_i : cmp_132 port map ( + eq => sig_313, + in0 => "001", + in1 => augh_main_i(2 downto 0) + ); + + cmp_136_i : cmp_136 port map ( + eq => sig_312, + in0 => "110", + in1 => sig_298(2 downto 0) + ); + + cmp_137_i : cmp_137 port map ( + eq => sig_311, + in0 => "101", + in1 => sig_298(2 downto 0) + ); + + cmp_138_i : cmp_138 port map ( + eq => sig_310, + in0 => "100", + in1 => sig_298(2 downto 0) + ); + + cmp_139_i : cmp_139 port map ( + eq => sig_309, + in0 => "011", + in1 => sig_298(2 downto 0) + ); + + cmp_140_i : cmp_140 port map ( + eq => sig_308, + in0 => "010", + in1 => sig_298(2 downto 0) + ); + + cmp_141_i : cmp_141 port map ( + eq => sig_307, + in0 => "001", + in1 => sig_298(2 downto 0) + ); + + cmp_142_i : cmp_142 port map ( + eq => sig_306, + in0 => "000", + in1 => sig_298(2 downto 0) + ); + + muxb_117_i : muxb_117 port map ( + in_sel => cp_en, + out_data => sig_305, + in_data0 => '0', + in_data1 => '1' + ); + + add_118_i : add_118 port map ( + result => sig_304, + in_a => psc_loop_reg_3, + in_b => "0000000000000001" + ); + + cmp_119_i : cmp_119 port map ( + ne => sig_303, + in0 => "0000000000000001", + in1 => psc_loop_reg_3 + ); + + muxb_121_i : muxb_121 port map ( + in_sel => not_122, + out_data => sig_302, + in_data0 => '0', + in_data1 => '1' + ); + + muxb_123_i : muxb_123 port map ( + in_sel => not_122, + out_data => sig_301, + in_data0 => '0', + in_data1 => '1' + ); + + sub_125_i : sub_125 port map ( + le => augh_test_1, + sign => '1', + result => sig_300, + in_a => augh_main_i, + in_b => "00000000000000000000000000000111" + ); + + cmp_126_i : cmp_126 port map ( + eq => sig_299, + in0 => "111", + in1 => augh_main_i(2 downto 0) + ); + + add_134_i : add_134 port map ( + result => sig_298, + in_a => augh_main_i, + in_b => "00000000000000000000000000000001" + ); + + sub_145_i : sub_145 port map ( + result => sig_297, + in_a => augh_main_max_iter(3 downto 0), + in_b => "0001" + ); + + cmp_146_i : cmp_146 port map ( + eq => sig_296, + in0 => "111", + in1 => sig_297(2 downto 0) + ); + + add_170_i : add_170 port map ( + result => sig_295, + in_a => sig_341, + in_b => sig_340 + ); + + cmp_174_i : cmp_174 port map ( + eq => sig_294, + in0 => "111", + in1 => augh_main_i(2 downto 0) + ); + + cmp_176_i : cmp_176 port map ( + eq => sig_293, + in0 => "110", + in1 => augh_main_i(2 downto 0) + ); + + cmp_178_i : cmp_178 port map ( + eq => sig_292, + in0 => "101", + in1 => augh_main_i(2 downto 0) + ); + + cmp_180_i : cmp_180 port map ( + eq => sig_291, + in0 => "100", + in1 => augh_main_i(2 downto 0) + ); + + cmp_187_i : cmp_187 port map ( + eq => sig_290, + in0 => "000", + in1 => augh_main_i(2 downto 0) + ); + + add_188_i : add_188 port map ( + result => sig_289, + in_a => augh_main_result, + in_b => sig_339 + ); + + sub_189_i : sub_189 port map ( + lt => augh_test_0, + sign => '1', + result => sig_288, + in_a => augh_main_i, + in_b => augh_main_max_iter + ); + + cmp_191_i : cmp_191 port map ( + eq => sig_287, + in0 => "111", + in1 => augh_main_i(2 downto 0) + ); + + cmp_198_i : cmp_198 port map ( + eq => sig_286, + in0 => "011", + in1 => augh_main_i(2 downto 0) + ); + + cmp_200_i : cmp_200 port map ( + eq => sig_285, + in0 => "010", + in1 => augh_main_i(2 downto 0) + ); + + cmp_202_i : cmp_202 port map ( + eq => sig_284, + in0 => "001", + in1 => augh_main_i(2 downto 0) + ); + + cmp_204_i : cmp_204 port map ( + eq => sig_283, + in0 => "000", + in1 => augh_main_i(2 downto 0) + ); + + add_214_i : add_214 port map ( + result => sig_282, + in_a => or_205, + in_b => augh_main_i(7 downto 0) + ); + + cmp_215_i : cmp_215 port map ( + eq => sig_281, + in0 => "001", + in1 => cp_id_reg_stable_5 + ); + + muxb_219_i : muxb_219 port map ( + in_sel => cp_en, + out_data => sig_280, + in_data0 => '0', + in_data1 => '1' + ); + + add_220_i : add_220 port map ( + result => sig_279, + in_a => psc_loop_reg_3, + in_b => "0000000000000001" + ); + + cmp_221_i : cmp_221 port map ( + ne => psc_loop_sig_12, + in0 => "0000000000000010", + in1 => psc_loop_reg_3 + ); + + cmp_111_i : cmp_111 port map ( + eq => test_cp_2_10, + in0 => "010", + in1 => cp_id_reg_stable_5 + ); + + cmp_113_i : cmp_113 port map ( + eq => sig_278, + in0 => "000", + in1 => cp_id_reg_stable_5 + ); + + cmp_216_i : cmp_216 port map ( + eq => sig_277, + in0 => "000", + in1 => cp_id_reg_stable_5 + ); + + cmp_217_i : cmp_217 port map ( + eq => sig_276, + in0 => "011", + in1 => cp_id_reg_stable_5 + ); + + cmp_218_i : cmp_218 port map ( + eq => sig_275, + in0 => "100", + in1 => cp_id_reg_stable_5 + ); + + fsm_15_i : fsm_15 port map ( + clock => sig_clock, + reset => sig_reset, + out3 => sig_274, + out157 => sig_273, + out159 => sig_272, + out160 => sig_271, + out171 => sig_270, + out172 => sig_269, + out173 => sig_268, + out175 => sig_267, + out178 => sig_266, + in0 => test_cp_4_6, + out0 => sig_265, + in5 => memextrct_loop_sig_14, + in6 => memextrct_loop_sig_13, + in7 => stdout_ack, + out35 => sig_264, + out39 => sig_263, + out40 => sig_262, + out41 => sig_261, + out44 => sig_260, + out46 => sig_259, + out140 => sig_258, + in8 => cp_en, + in9 => stdin_ack, + in10 => augh_test_1, + in11 => augh_test_0, + in12 => cp_rest, + in13 => sig_start, + in14 => psc_loop_sig_12, + out65 => sig_257, + in1 => test_cp_3_7, + in2 => test_cp_0_8, + in3 => test_cp_1_9, + in4 => test_cp_2_10, + out225 => sig_256, + out227 => sig_255, + out231 => sig_254, + out235 => sig_253, + out236 => sig_252, + out237 => sig_251, + out238 => sig_250, + out97 => sig_249, + out98 => sig_248, + out101 => sig_247, + out102 => sig_246, + out124 => sig_245, + out125 => sig_244, + out80 => sig_243, + out81 => sig_242, + out84 => sig_241, + out86 => sig_240, + out88 => sig_239, + out93 => sig_238, + out94 => sig_237 + ); + + cmp_112_i : cmp_112 port map ( + eq => sig_236, + in0 => "001", + in1 => cp_id_reg_stable_5 + ); + + cmp_114_i : cmp_114 port map ( + eq => sig_235, + in0 => "011", + in1 => cp_id_reg_stable_5 + ); + + cmp_115_i : cmp_115 port map ( + eq => sig_234, + in0 => "100", + in1 => cp_id_reg_stable_5 + ); + + cmp_148_i : cmp_148 port map ( + eq => sig_233, + in0 => "110", + in1 => sig_297(2 downto 0) + ); + + cmp_150_i : cmp_150 port map ( + eq => sig_232, + in0 => "101", + in1 => sig_297(2 downto 0) + ); + + cmp_152_i : cmp_152 port map ( + eq => sig_231, + in0 => "100", + in1 => sig_297(2 downto 0) + ); + + cmp_154_i : cmp_154 port map ( + eq => sig_230, + in0 => "011", + in1 => sig_297(2 downto 0) + ); + + cmp_156_i : cmp_156 port map ( + eq => sig_229, + in0 => "010", + in1 => sig_297(2 downto 0) + ); + + cmp_158_i : cmp_158 port map ( + eq => sig_228, + in0 => "001", + in1 => sig_297(2 downto 0) + ); + + cmp_160_i : cmp_160 port map ( + eq => sig_227, + in0 => "000", + in1 => sig_297(2 downto 0) + ); + + cmp_127_i : cmp_127 port map ( + eq => sig_226, + in0 => "110", + in1 => augh_main_i(2 downto 0) + ); + + cmp_129_i : cmp_129 port map ( + eq => sig_225, + in0 => "100", + in1 => augh_main_i(2 downto 0) + ); + + cmp_131_i : cmp_131 port map ( + eq => sig_224, + in0 => "010", + in1 => augh_main_i(2 downto 0) + ); + + cmp_133_i : cmp_133 port map ( + eq => sig_223, + in0 => "000", + in1 => augh_main_i(2 downto 0) + ); + + cmp_135_i : cmp_135 port map ( + eq => sig_222, + in0 => "111", + in1 => sig_298(2 downto 0) + ); + + -- Behaviour of component 'mux_25' model 'mux' + mux_25 <= + (sig_274 and sig_234) or + (sig_254 and sig_275); + + -- Behaviour of component 'mux_26' model 'mux' + mux_26 <= + (repeat(3, sig_243) and "010") or + (repeat(3, sig_253) and cp_din(2 downto 0)) or + (repeat(3, sig_240) and "001") or + (repeat(3, sig_271) and "011") or + (repeat(3, sig_267) and "100"); + + -- Behaviour of component 'mux_27' model 'mux' + mux_27 <= + (sig_242 and '1') or + (sig_252 and cp_rest); + + -- Behaviour of component 'mux_28' model 'mux' + mux_28 <= + (repeat(3, sig_243) and "010") or + (repeat(3, sig_251) and augh_main_result(2 downto 0)) or + (repeat(3, sig_240) and "001") or + (repeat(3, sig_271) and "011") or + (repeat(3, sig_267) and "100"); + + -- Behaviour of component 'mux_29' model 'mux' + mux_29 <= + (sig_242 and '1') or + (sig_250 and cp_en); + + -- Behaviour of component 'mux_30' model 'mux' + mux_30 <= + (repeat(16, sig_262) and sig_304) or + (repeat(16, sig_251) and sig_279); + + -- Behaviour of component 'mux_31' model 'mux' + mux_31 <= + (sig_261 and cp_en) or + (sig_260 and '1'); + + -- Behaviour of component 'mux_32' model 'mux' + mux_32 <= + (repeat(8, sig_263) and cp_din(7 downto 0)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_33' model 'mux' + mux_33 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_34' model 'mux' + mux_34 <= + (sig_264 and and_116) or + (sig_266 and and_190); + + -- Behaviour of component 'mux_35' model 'mux' + mux_35 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_36' model 'mux' + mux_36 <= + (repeat(8, sig_263) and cp_din(15 downto 8)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_37' model 'mux' + mux_37 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_38' model 'mux' + mux_38 <= + (sig_264 and and_116) or + (sig_266 and and_192); + + -- Behaviour of component 'mux_39' model 'mux' + mux_39 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_40' model 'mux' + mux_40 <= + (repeat(8, sig_263) and cp_din(23 downto 16)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_41' model 'mux' + mux_41 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_42' model 'mux' + mux_42 <= + (sig_264 and and_116) or + (sig_266 and and_194); + + -- Behaviour of component 'mux_43' model 'mux' + mux_43 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_23' model 'mux' + mux_23 <= + (sig_274 and sig_278) or + (sig_254 and sig_277); + + -- Behaviour of component 'mux_24' model 'mux' + mux_24 <= + (sig_274 and sig_235) or + (sig_254 and sig_276); + + -- Behaviour of component 'mux_44' model 'mux' + mux_44 <= + (repeat(8, sig_263) and cp_din(31 downto 24)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_45' model 'mux' + mux_45 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_249 and '1') or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_46' model 'mux' + mux_46 <= + (sig_264 and and_116) or + (sig_248 and '1') or + (sig_266 and and_196); + + -- Behaviour of component 'mux_47' model 'mux' + mux_47 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_48' model 'mux' + mux_48 <= + (repeat(8, sig_263) and cp_din(39 downto 32)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_49' model 'mux' + mux_49 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_50' model 'mux' + mux_50 <= + (sig_264 and and_116) or + (sig_266 and and_197); + + -- Behaviour of component 'mux_51' model 'mux' + mux_51 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_52' model 'mux' + mux_52 <= + (repeat(8, sig_263) and cp_din(47 downto 40)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_53' model 'mux' + mux_53 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_54' model 'mux' + mux_54 <= + (sig_264 and and_116) or + (sig_266 and and_199); + + -- Behaviour of component 'mux_55' model 'mux' + mux_55 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_56' model 'mux' + mux_56 <= + (repeat(8, sig_263) and cp_din(55 downto 48)) or + (repeat(8, sig_267) and sig_282) or + (repeat(8, sig_256) and "00000011"); + + -- Behaviour of component 'mux_57' model 'mux' + mux_57 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_58' model 'mux' + mux_58 <= + (sig_264 and and_116) or + (sig_266 and and_201) or + (sig_255 and '1'); + + -- Behaviour of component 'mux_59' model 'mux' + mux_59 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_60' model 'mux' + mux_60 <= + (repeat(8, sig_263) and cp_din(63 downto 56)) or + (repeat(8, sig_267) and sig_282); + + -- Behaviour of component 'mux_61' model 'mux' + mux_61 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_62' model 'mux' + mux_62 <= + (sig_264 and and_116) or + (sig_266 and and_203); + + -- Behaviour of component 'mux_63' model 'mux' + mux_63 <= + (sig_263 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_267 and augh_main_i(3)); + + -- Behaviour of component 'mux_64' model 'mux' + mux_64 <= + (repeat(32, sig_269) and sig_298) or + (repeat(32, sig_251) and augh_main_std_addition); + + -- Behaviour of component 'mux_65' model 'mux' + mux_65 <= + (sig_272 and '1') or + (sig_268 and not_122) or + (sig_250 and cp_en); + + -- Behaviour of component 'mux_66' model 'mux' + mux_66 <= + (repeat(32, sig_258) and sig_322) or + (repeat(32, sig_271) and sig_289) or + (repeat(32, sig_251) and augh_main_max_iter); + + -- Behaviour of component 'mux_67' model 'mux' + mux_67 <= + (sig_273 and '1') or + (sig_270 and not_122) or + (sig_250 and cp_en); + + -- Behaviour of component 'mux_68' model 'mux' + mux_68 <= + (repeat(32, sig_237) and stdin_data) or + (repeat(32, sig_251) and cp_din(63 downto 32)); + + -- Behaviour of component 'mux_69' model 'mux' + mux_69 <= + (sig_238 and not_122) or + (sig_250 and cp_en); + + -- Behaviour of component 'mux_70' model 'mux' + mux_70 <= + (repeat(32, sig_240) and stdin_data) or + (repeat(32, sig_251) and cp_din(31 downto 0)); + + -- Behaviour of component 'mux_71' model 'mux' + mux_71 <= + (sig_239 and not_122) or + (sig_250 and cp_en); + + -- Behaviour of component 'mux_72' model 'mux' + mux_72 <= + (repeat(8, sig_259) and cp_din(7 downto 0)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_73' model 'mux' + mux_73 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_74' model 'mux' + mux_74 <= + (sig_257 and and_116) or + (sig_246 and sig_299) or + (sig_244 and sig_222) or + (sig_266 and and_190); + + -- Behaviour of component 'mux_75' model 'mux' + mux_75 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_76' model 'mux' + mux_76 <= + (repeat(8, sig_259) and cp_din(15 downto 8)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_77' model 'mux' + mux_77 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_78' model 'mux' + mux_78 <= + (sig_257 and and_116) or + (sig_246 and sig_226) or + (sig_244 and sig_312) or + (sig_266 and and_192); + + -- Behaviour of component 'mux_79' model 'mux' + mux_79 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_80' model 'mux' + mux_80 <= + (repeat(8, sig_259) and cp_din(23 downto 16)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)) or + (repeat(8, sig_256) and "00001100"); + + -- Behaviour of component 'mux_20' model 'mux' + mux_20 <= + (sig_250 and cp_en); + + -- Behaviour of component 'mux_22' model 'mux' + mux_22 <= + (sig_274 and sig_236) or + (sig_254 and sig_281); + + -- Behaviour of component 'and_163' model 'and' + and_163 <= + sig_324 and + repeat(8, sig_233); + + -- Behaviour of component 'and_164' model 'and' + and_164 <= + sig_325 and + repeat(8, sig_232); + + -- Behaviour of component 'and_165' model 'and' + and_165 <= + sig_326 and + repeat(8, sig_231); + + -- Behaviour of component 'and_166' model 'and' + and_166 <= + sig_327 and + repeat(8, sig_230); + + -- Behaviour of component 'and_167' model 'and' + and_167 <= + sig_328 and + repeat(8, sig_229); + + -- Behaviour of component 'and_168' model 'and' + and_168 <= + sig_329 and + repeat(8, sig_228); + + -- Behaviour of component 'and_169' model 'and' + and_169 <= + sig_330 and + repeat(8, sig_227); + + -- Behaviour of component 'and_182' model 'and' + and_182 <= + sig_336 and + repeat(8, sig_321); + + -- Behaviour of component 'and_184' model 'and' + and_184 <= + sig_337 and + repeat(8, sig_320); + + -- Behaviour of component 'and_186' model 'and' + and_186 <= + sig_338 and + repeat(8, sig_290); + + -- Behaviour of component 'and_192' model 'and' + and_192 <= + not_122 and + sig_319; + + -- Behaviour of component 'and_194' model 'and' + and_194 <= + not_122 and + sig_318; + + -- Behaviour of component 'and_196' model 'and' + and_196 <= + not_122 and + sig_225; + + -- Behaviour of component 'mux_81' model 'mux' + mux_81 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_82' model 'mux' + mux_82 <= + (sig_257 and and_116) or + (sig_246 and sig_315) or + (sig_244 and sig_311) or + (sig_266 and and_194) or + (sig_255 and '1'); + + -- Behaviour of component 'mux_83' model 'mux' + mux_83 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_84' model 'mux' + mux_84 <= + (repeat(8, sig_259) and cp_din(31 downto 24)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_85' model 'mux' + mux_85 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_86' model 'mux' + mux_86 <= + (sig_257 and and_116) or + (sig_246 and sig_225) or + (sig_244 and sig_310) or + (sig_266 and and_196); + + -- Behaviour of component 'mux_87' model 'mux' + mux_87 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_88' model 'mux' + mux_88 <= + (repeat(8, sig_259) and cp_din(39 downto 32)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_89' model 'mux' + mux_89 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_90' model 'mux' + mux_90 <= + (sig_257 and and_116) or + (sig_246 and sig_314) or + (sig_244 and sig_309) or + (sig_266 and and_197); + + -- Behaviour of component 'mux_91' model 'mux' + mux_91 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_92' model 'mux' + mux_92 <= + (repeat(8, sig_259) and cp_din(47 downto 40)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_93' model 'mux' + mux_93 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_94' model 'mux' + mux_94 <= + (sig_257 and and_116) or + (sig_246 and sig_224) or + (sig_244 and sig_308) or + (sig_266 and and_199); + + -- Behaviour of component 'mux_95' model 'mux' + mux_95 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_96' model 'mux' + mux_96 <= + (repeat(8, sig_259) and cp_din(55 downto 48)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_97' model 'mux' + mux_97 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_98' model 'mux' + mux_98 <= + (sig_257 and and_116) or + (sig_246 and sig_313) or + (sig_244 and sig_307) or + (sig_266 and and_201); + + -- Behaviour of component 'mux_99' model 'mux' + mux_99 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_100' model 'mux' + mux_100 <= + (repeat(8, sig_259) and cp_din(63 downto 56)) or + (repeat(8, sig_267) and augh_main_i(7 downto 0)); + + -- Behaviour of component 'mux_101' model 'mux' + mux_101 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_247 and augh_main_i(3)) or + (sig_245 and sig_298(3)); + + -- Behaviour of component 'mux_102' model 'mux' + mux_102 <= + (sig_257 and and_116) or + (sig_246 and sig_223) or + (sig_244 and sig_306) or + (sig_266 and and_203); + + -- Behaviour of component 'mux_103' model 'mux' + mux_103 <= + (sig_259 and psc_loop_reg_3(0)) or + (sig_258 and sig_297(3)) or + (sig_271 and augh_main_i(3)); + + -- Behaviour of component 'mux_106' model 'mux' + mux_106 <= + (sig_239 and sig_301) or + (sig_238 and sig_316); + + -- Behaviour of component 'mux_108' model 'mux' + mux_108 <= + (sig_241 and sig_302); + + -- Behaviour of component 'mux_109' model 'mux' + mux_109 <= + (repeat(64, sig_263) and (sig_330 & sig_329 & sig_328 & sig_327 & sig_326 & sig_325 & sig_324 & sig_323)) or + (repeat(64, sig_259) and (sig_338 & sig_337 & sig_336 & sig_335 & sig_334 & sig_333 & sig_332 & sig_331)) or + (repeat(64, sig_251) and (psc_stuff_reg_11 & cp_id_reg_4)); + + -- Behaviour of component 'mux_110' model 'mux' + mux_110 <= + (sig_265 and '1') or + (sig_263 and sig_305) or + (sig_259 and sig_317) or + (sig_251 and sig_280); + + -- Behaviour of component 'and_116' model 'and' + and_116 <= + cp_en and + cp_rest; + + -- Behaviour of component 'not_122' model 'not' + not_122 <= not ( + cp_en + ); + + -- Behaviour of component 'or_143' model 'or' + or_143 <= + and_144 or + and_155 or + and_157 or + and_159 or + and_147 or + and_149 or + and_151 or + and_153; + + -- Behaviour of component 'and_147' model 'and' + and_147 <= + sig_332 and + repeat(8, sig_233); + + -- Behaviour of component 'and_149' model 'and' + and_149 <= + sig_333 and + repeat(8, sig_232); + + -- Behaviour of component 'and_151' model 'and' + and_151 <= + sig_334 and + repeat(8, sig_231); + + -- Behaviour of component 'and_153' model 'and' + and_153 <= + sig_335 and + repeat(8, sig_230); + + -- Behaviour of component 'and_155' model 'and' + and_155 <= + sig_336 and + repeat(8, sig_229); + + -- Behaviour of component 'and_157' model 'and' + and_157 <= + sig_337 and + repeat(8, sig_228); + + -- Behaviour of component 'and_159' model 'and' + and_159 <= + sig_338 and + repeat(8, sig_227); + + -- Behaviour of component 'or_161' model 'or' + or_161 <= + and_162 or + and_167 or + and_168 or + and_169 or + and_163 or + and_164 or + and_165 or + and_166; + + -- Behaviour of component 'and_162' model 'and' + and_162 <= + sig_323 and + repeat(8, sig_296); + + -- Behaviour of component 'or_172' model 'or' + or_172 <= + and_173 or + and_182 or + and_184 or + and_186 or + and_175 or + and_177 or + and_179 or + and_181; + + -- Behaviour of component 'and_173' model 'and' + and_173 <= + sig_331 and + repeat(8, sig_294); + + -- Behaviour of component 'and_175' model 'and' + and_175 <= + sig_332 and + repeat(8, sig_293); + + -- Behaviour of component 'and_177' model 'and' + and_177 <= + sig_333 and + repeat(8, sig_292); + + -- Behaviour of component 'and_179' model 'and' + and_179 <= + sig_334 and + repeat(8, sig_291); + + -- Behaviour of component 'and_181' model 'and' + and_181 <= + sig_335 and + repeat(8, sig_314); + + -- Behaviour of component 'and_190' model 'and' + and_190 <= + not_122 and + sig_287; + + -- Behaviour of component 'and_197' model 'and' + and_197 <= + not_122 and + sig_286; + + -- Behaviour of component 'and_199' model 'and' + and_199 <= + not_122 and + sig_285; + + -- Behaviour of component 'and_201' model 'and' + and_201 <= + not_122 and + sig_284; + + -- Behaviour of component 'and_203' model 'and' + and_203 <= + not_122 and + sig_283; + + -- Behaviour of component 'or_205' model 'or' + or_205 <= + and_206 or + and_211 or + and_212 or + and_213 or + and_207 or + and_208 or + and_209 or + and_210; + + -- Behaviour of component 'and_206' model 'and' + and_206 <= + sig_323 and + repeat(8, sig_287); + + -- Behaviour of component 'and_207' model 'and' + and_207 <= + sig_324 and + repeat(8, sig_319); + + -- Behaviour of component 'and_208' model 'and' + and_208 <= + sig_325 and + repeat(8, sig_318); + + -- Behaviour of component 'and_209' model 'and' + and_209 <= + sig_326 and + repeat(8, sig_225); + + -- Behaviour of component 'and_210' model 'and' + and_210 <= + sig_327 and + repeat(8, sig_286); + + -- Behaviour of component 'and_211' model 'and' + and_211 <= + sig_328 and + repeat(8, sig_285); + + -- Behaviour of component 'and_212' model 'and' + and_212 <= + sig_329 and + repeat(8, sig_284); + + -- Behaviour of component 'and_213' model 'and' + and_213 <= + sig_330 and + repeat(8, sig_283); + + -- Behaviour of component 'and_144' model 'and' + and_144 <= + sig_331 and + repeat(8, sig_296); + + -- Behaviour of all components of model 'reg' + -- Registers with clock = sig_clock and reset = sig_reset active '1' + process(sig_clock, sig_reset) + begin + if sig_reset = '1' then + psc_stuff_reg_11 <= "0000000000000000000000000000000000000000000000000000000000000"; + else + if rising_edge(sig_clock) then + if mux_20 = '1' then + psc_stuff_reg_11 <= augh_main_i & augh_main_result(31 downto 3); + end if; + end if; + end if; + end process; + -- Registers with clock = sig_clock and no reset + process(sig_clock) + begin + if rising_edge(sig_clock) then + if mux_27 = '1' then + cp_id_reg_stable_5 <= mux_26; + end if; + if mux_29 = '1' then + cp_id_reg_4 <= mux_28; + end if; + if mux_31 = '1' then + psc_loop_reg_3 <= mux_30; + end if; + if mux_65 = '1' then + augh_main_i <= mux_64; + end if; + if mux_67 = '1' then + augh_main_result <= mux_66; + end if; + if mux_69 = '1' then + augh_main_std_addition <= mux_68; + end if; + if mux_71 = '1' then + augh_main_max_iter <= mux_70; + end if; + end if; + end process; + + -- Remaining signal assignments + -- Those who are not assigned by component instantiation + + sig_clock <= clock; + sig_reset <= reset; + sig_start <= start; + test_cp_4_6 <= mux_25; + test_cp_3_7 <= mux_24; + test_cp_0_8 <= mux_23; + test_cp_1_9 <= mux_22; + memextrct_loop_sig_13 <= sig_303; + memextrct_loop_sig_14 <= sig_303; + sig_339 <= repeat(24, or_172(7)) & or_172; + sig_340 <= or_161(7) & or_161; + sig_341 <= or_143(7) & or_143; + sig_342 <= repeat(23, sig_295(8)) & sig_295; + + -- Remaining top-level ports assignments + -- Those who are not assigned by component instantiation + + stdin_rdy <= mux_106; + stdout_data <= augh_main_result; + stdout_rdy <= mux_108; + cp_dout <= mux_109; + cp_ok <= mux_110; + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split0.vhd b/testsuite/gna/issue50/vector.d/v_split0.vhd new file mode 100644 index 000000000..e95973e01 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split0.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split0 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split0; +architecture augh of v_split0 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split1.vhd b/testsuite/gna/issue50/vector.d/v_split1.vhd new file mode 100644 index 000000000..537758796 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split1.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split1 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split1; +architecture augh of v_split1 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split2.vhd b/testsuite/gna/issue50/vector.d/v_split2.vhd new file mode 100644 index 000000000..3ec8ce48c --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split2.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split2 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split2; +architecture augh of v_split2 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split3.vhd b/testsuite/gna/issue50/vector.d/v_split3.vhd new file mode 100644 index 000000000..a2a569c3b --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split3.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split3 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split3; +architecture augh of v_split3 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split4.vhd b/testsuite/gna/issue50/vector.d/v_split4.vhd new file mode 100644 index 000000000..f48a53a47 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split4.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split4 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split4; +architecture augh of v_split4 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split5.vhd b/testsuite/gna/issue50/vector.d/v_split5.vhd new file mode 100644 index 000000000..ea9acd5a5 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split5.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split5 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split5; +architecture augh of v_split5 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split6.vhd b/testsuite/gna/issue50/vector.d/v_split6.vhd new file mode 100644 index 000000000..98e87b9cc --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split6.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split6 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split6; +architecture augh of v_split6 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/v_split7.vhd b/testsuite/gna/issue50/vector.d/v_split7.vhd new file mode 100644 index 000000000..ff89b3c21 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/v_split7.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity v_split7 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end v_split7; +architecture augh of v_split7 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split0.vhd b/testsuite/gna/issue50/vector.d/w_split0.vhd new file mode 100644 index 000000000..0fcb022f3 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split0.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split0 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split0; +architecture augh of w_split0 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split1.vhd b/testsuite/gna/issue50/vector.d/w_split1.vhd new file mode 100644 index 000000000..aa72b9f55 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split1.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split1 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split1; +architecture augh of w_split1 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split2.vhd b/testsuite/gna/issue50/vector.d/w_split2.vhd new file mode 100644 index 000000000..b23549ac2 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split2.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split2 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split2; +architecture augh of w_split2 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split3.vhd b/testsuite/gna/issue50/vector.d/w_split3.vhd new file mode 100644 index 000000000..446b4ee14 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split3.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split3 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split3; +architecture augh of w_split3 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000000" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split4.vhd b/testsuite/gna/issue50/vector.d/w_split4.vhd new file mode 100644 index 000000000..0be33beb5 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split4.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split4 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split4; +architecture augh of w_split4 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split5.vhd b/testsuite/gna/issue50/vector.d/w_split5.vhd new file mode 100644 index 000000000..dd447b296 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split5.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split5 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split5; +architecture augh of w_split5 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split6.vhd b/testsuite/gna/issue50/vector.d/w_split6.vhd new file mode 100644 index 000000000..e00068742 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split6.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split6 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split6; +architecture augh of w_split6 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/issue50/vector.d/w_split7.vhd b/testsuite/gna/issue50/vector.d/w_split7.vhd new file mode 100644 index 000000000..046b02597 --- /dev/null +++ b/testsuite/gna/issue50/vector.d/w_split7.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity w_split7 is + port ( + clk : in std_logic; + ra0_data : out std_logic_vector(7 downto 0); + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic; + wa0_en : in std_logic; + ra0_addr : in std_logic + ); +end w_split7; +architecture augh of w_split7 is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); + signal ram : ram_type := ( + "00000111", "00000111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; |