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-rw-r--r--testsuite/gna/issue648/repro.vhdl12
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diff --git a/testsuite/gna/issue648/repro.vhdl b/testsuite/gna/issue648/repro.vhdl
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+++ b/testsuite/gna/issue648/repro.vhdl
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+entity repro is
+end entity;
+
+architecture h of repro is
+ constant L :positive := 9 + now / 1 ns;
+ signal s :bit_vector(31 downto 0);
+ alias a :bit_vector(L-1 downto 2) is s(L-1 downto 2);
+ signal b :bit_vector(L-1 downto 2);
+begin
+ a <= b;
+end architecture;
+