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* vhdl-sem_expr.adb(is_string_type): check character type.Tristan Gingold2022-10-161-1/+3
| | | | Fix #2217
* testsuite/gna: add a test for #2219Tristan Gingold2022-10-142-0/+39
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* vhdl-parse.adb: handle external names as assignment target.Tristan Gingold2022-10-141-2/+4
| | | | Fix #2219
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
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* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
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* synth: avoid extra conversion during alias elaborationTristan Gingold2022-10-141-6/+4
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* simul: fix spurious error about multiple driversTristan Gingold2022-10-141-0/+2
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* simul: handle delayed attributeTristan Gingold2022-10-142-6/+66
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* synth: handle alias of access objects.Tristan Gingold2022-10-131-1/+1
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* simul: handle last_event and last_activeTristan Gingold2022-10-133-4/+114
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* elab-vhd_expr: handle more cases in exec_type_of_objectTristan Gingold2022-10-131-1/+4
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* simul-vhdl_simul: keep default value of collapsed signalsTristan Gingold2022-10-131-1/+10
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* simul-vhdl_elab: fix crash on association with implicit signalsTristan Gingold2022-10-131-1/+4
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* simul: fix a crash due to missing strideTristan Gingold2022-10-131-5/+7
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* testsuite/synth: add a test for #2214Tristan Gingold2022-10-134-0/+346
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* synth-vhdl_stmts(synth_verification_unit): always set instance_pool.Tristan Gingold2022-10-131-1/+3
| | | | Fix #2214
* testsuite/suite_driver.sh: disp log in case of failureTristan Gingold2022-10-111-1/+2
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* synth: fix crashes on scalar attribute with anonymous subtype.Tristan Gingold2022-10-101-2/+2
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* testsuite/gna: add a test for #2212Tristan Gingold2022-10-102-0/+33
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* vhdl-canon: avoid a crash on optionnal condition. Fix #2212Tristan Gingold2022-10-101-1/+1
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* simul: handle guarded concurrent assignmentsTristan Gingold2022-10-101-14/+32
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* simul-vhdl_debug: handle state before elaborationTristan Gingold2022-10-101-0/+8
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* testsuite/gna: add a test for #2209Tristan Gingold2022-10-082-0/+19
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* vhdl-sem.adb(are_trees_equal): handle parenthesis expressions.Tristan Gingold2022-10-081-0/+4
| | | | Fix #2209
* simul: signal attributes in actualsTristan Gingold2022-10-061-2/+4
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* simul: complete concurrent procedure callsTristan Gingold2022-10-063-29/+43
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* simul: fix initial value of record signalsTristan Gingold2022-10-061-2/+2
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* simul: recompute object alias offsetsTristan Gingold2022-10-061-1/+14
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* simul: fix signal attribute or guard as actual in connectionsTristan Gingold2022-10-062-11/+15
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* simul: improve debugger (display of signals value)Tristan Gingold2022-10-064-38/+74
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* simul: handle suspendable procedure call from sensitized process.Tristan Gingold2022-10-052-3/+11
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* testsuite/synth: add a reproducer for #2205Tristan Gingold2022-10-042-0/+40
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* elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205Tristan Gingold2022-10-041-2/+4
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* testsuite/synth: add a test for #2204Tristan Gingold2022-10-036-0/+158
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* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-033-17/+46
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* gh action: replace ubuntu 18 by ubuntu 22 (without docker)Tristan Gingold2022-10-032-31/+51
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* workflow: back to ubuntu 18.Tristan Gingold2022-10-031-3/+3
| | | | Requires more work, done in a branch
* workflow: use llvm-14 on unbuntu-22Tristan Gingold2022-10-021-1/+1
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* workflows: tentatively build on ubuntu22Tristan Gingold2022-10-022-4/+4
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* github actions: use llvm14 on macosxTristan Gingold2022-10-021-1/+1
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* translate, grt: add lib function for div and rem.Tristan Gingold2022-10-026-8/+148
| | | | | Do not rely on hardware exceptions to catch division by 0, they are caught in windows by the c handler and not propagated
* synth: improve error recoveryTristan Gingold2022-10-021-0/+3
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* synth: detect division by 0, handle universal real/integer divisionTristan Gingold2022-10-021-3/+23
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* testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-022-0/+37
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* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
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* synth: avoid a crash on literal overflowTristan Gingold2022-10-011-1/+10
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* synth: avoid on crash on overflow in rangesTristan Gingold2022-10-011-0/+8
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* synth: improve handling of individual generic associationsTristan Gingold2022-10-011-17/+22
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* simul: finalize empty proceduresTristan Gingold2022-10-011-9/+11
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* simul: minor rewriteTristan Gingold2022-10-011-3/+2
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