iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	4	-100/+157
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*	revert "configure: fix setting abs_srcdir on MSYS2/MINGW" (#911) (#914)	1138-4EB	2019-09-02	1	-6/+5
\| \| \|	This reverts commit 7b02418ec508af9e340cad5e93ab06e8f1fb84c8.
*	Fix UPF (#905)	1138-4EB	2019-09-01	4	-5/+21
\| \| \| \| \| \|	* add test for UPF * fix: add UPF when openieee=false too
*	Fix configure (#911)	1138-4EB	2019-09-01	1	-216/+222
\| \| \| \| \| \| \| \| \| \| \| \|	* configure: fix indentation * configure: add comment about using 'cmp -n' * configure: check if 'cmp' is available * configure: fix setting abs_srcdir on MSYS2/MINGW * configure: fix comment
*	fix(configure): ignore line ending when comparing ghdl_version and ↵	1138-4EB	2019-09-01	1	-1/+1
\| \| \| \|	libghdl_version (#910)
*	readme: fix refs to 'Building' (#909)	1138-4EB	2019-08-31	1	-3/+3
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*	[doc] Update section 'Getting GHDL' (#906)	1138-4EB	2019-08-31	21	-425/+268
\| \| \| \| \| \| \| \|	* doc: fix version extraction from 'configure' * doc: update section 'Getting GHDL' * readme: update
*	Merge pull request #907 from sharkcz/llvm-fix	tgingold	2019-08-31	1	-1/+1
\|\ \| \| \| \|	fix llvm build with synth enabled
\| *	fix llvm build with synth enabled	Dan Horák	2019-08-31	1	-1/+1
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*	synth: remove insert gate.	Tristan Gingold	2019-08-31	4	-70/+0
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*	synth: improve synth_uresize.	Tristan Gingold	2019-08-31	3	-26/+50
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*	synth: elab subprogram interfaces subtype	Tristan Gingold	2019-08-31	1	-2/+13
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*	[PATCH] synth-environment: fix thinkos.	Tristan Gingold	2019-08-31	8	-15/+231
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*	synth: add physical division (#904)	tgingold	2019-08-30	3	-1/+36
\|\ \| \| \| \| \| \| \| \| \| \|	* synth: added division of physical type * testsuite/synth: added test for the physical division
\| *	testsuite/synth: added test for the physical division	Martin Doerfelt	2019-08-30	2	-0/+25
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\| *	synth: added division of physical type	Martin Doerfelt	2019-08-30	1	-1/+11
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* \|	synth: add support for --synth on llvm, link with -lm.	Tristan Gingold	2019-08-30	2	-0/+6
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* \|	synth: fix type elaboration of interfaces.	Tristan Gingold	2019-08-30	1	-2/+0
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* \|	synth: remove unused const gates.	Tristan Gingold	2019-08-30	2	-13/+5
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* \|	vhdl-annotations: ignore conditional variable assignment.	Tristan Gingold	2019-08-30	1	-1/+2
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* \|	vhdl-annotate: handle shared anonymous subtype in interfaces.	Tristan Gingold	2019-08-30	1	-1/+4
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* \|	synth: ignore report statement.	Tristan Gingold	2019-08-30	1	-0/+2
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* \|	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	4	-196/+241
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* \|	std_names: add std_match	Tristan Gingold	2019-08-30	2	-3/+5
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* \|	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	5	-114/+137
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* \|	synth: handle enumeration subtype in ranges.	Tristan Gingold	2019-08-30	1	-1/+2
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* \|	synth: fix named association in record aggregate.	Tristan Gingold	2019-08-30	1	-1/+3
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*	testsuite/synth: add testcase for records. Temporary disable stmt01	Tristan Gingold	2019-08-29	5	-0/+168
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*	synth: add support for record types.	Tristan Gingold	2019-08-29	13	-82/+361
\| \| \| \|	(WIP: need to fix regression of stmt01).
*	synth: Integer operators (#902)	marph91	2019-08-28	3	-0/+47
\| \| \| \| \| \| \| \|	* synth: added missing integer operators I. e. inequality and remainder. * testsuite/synth: added testcase for the missing integer operators
*	testsuite/synth: testcase for conditional signal assignment.	Tristan Gingold	2019-08-27	3	-0/+61
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*	synth: support sequential conditional signal assignment.	Tristan Gingold	2019-08-27	2	-0/+3
\| \| \| \|	Fix tgingold/ghdlsynth-beta#40
*	testsuite/synth: add cases for assign.	Tristan Gingold	2019-08-27	4	-4/+62
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*	testsuite/synth: add asgn01	Tristan Gingold	2019-08-27	5	-0/+124
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*	synth: rework partial assignments	Tristan Gingold	2019-08-27	10	-182/+608
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*	netlists-disp_vhdl: do not used literals for prefixes.	Tristan Gingold	2019-08-27	1	-12/+53
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*	Makefile.in: Add .NOTPARALLEL. For #888	Tristan Gingold	2019-08-27	1	-0/+9
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*	testsuite/synth: add fsm02 test.	Tristan Gingold	2019-08-27	5	-0/+181
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*	ignore restrict in simulation (#897)	Pepijn de Vos	2019-08-20	2	-18/+17
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*	synth: add support for constant exponentiation.	Tristan Gingold	2019-08-20	1	-0/+10
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*	synth: set name to assert/assume gates.	Tristan Gingold	2019-08-20	4	-12/+44
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*	netlist: fix minor pasto.	Tristan Gingold	2019-08-20	1	-1/+1
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*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	7	-6/+77
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*	vhdl psl: fully scan PSL keywords in scanner.	Tristan Gingold	2019-08-20	7	-67/+148
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*	vhdl-prints: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	1	-0/+7
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*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2019-08-20	2	-0/+13
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*	vhdl: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	3	-13/+53
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*	vhdl-prints: handle verification units.	Tristan Gingold	2019-08-20	1	-318/+354
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*	testsuite/synth: add a test for assume directive in verification units.	Tristan Gingold	2019-08-20	2	-2/+11
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*	vhdl: handle assume in verification units.	Tristan Gingold	2019-08-20	5	-1/+11
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