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using
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Synthesis.rst
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Author
Age
Files
Lines
*
doc: document --out=verilog for synth
Tristan Gingold
2021-04-28
1
-3
/
+6
*
doc: style, use 'file...' consistently
umarcor
2021-04-22
1
-1
/
+1
*
doc: style, use '[options...]' consistently
umarcor
2021-04-22
1
-3
/
+3
*
doc/synth: clarify that we need '-e' for resolving the ambiguity between a un...
umarcor
2021-04-22
1
-13
/
+21
*
doc: add/rename '[library.]top_unit [arch]', style (849a25e0)
umarcor
2021-04-22
1
-34
/
+37
*
doc/using: document synth option '--out' (#1705)
Unai Martinez-Corral
2021-03-31
1
-7
/
+26
*
doc/using/Synthesis: style
umarcor
2021-01-16
1
-16
/
+16
*
synth: add option to treat asserts as assumes and vice-versa
tmeissner
2021-01-02
1
-1
/
+28
*
doc: add 'Convert (V)HDL to other formats'
eine
2020-10-09
1
-21
/
+72
*
doc: fix pasto
eine
2020-10-08
1
-1
/
+1
*
doc: fix refs in 'Synthesis options'
eine
2020-10-08
1
-3
/
+4
*
Synth doc: add infos about synth specific options, related to 667ab51
tmeissner
2020-10-07
1
-0
/
+44
*
doc: document synthesis/translate pragmas
eine
2020-07-19
1
-0
/
+11
*
doc: split 'Interfacing to other languages' to ghdl/ghdl-cosim (#1216)
umarcor
2020-04-14
1
-1
/
+1
*
update doc (synth, overview, generics, etc.) (#1205)
umarcor
2020-04-10
1
-0
/
+67