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* vhdl: recognize find_leftmost/find_rightmost. For #1460Tristan Gingold2020-09-161-0/+2
* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-071-0/+2
* vhdl: add force and release tokens. For #1416Tristan Gingold2020-08-011-2/+2
* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-191-0/+3
* std_names: remove extra blank.Tristan Gingold2020-06-061-1/+1
* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-111-0/+1
* vhdl: handle pragma synthesis_on/synthesis_off.Tristan Gingold2020-04-111-0/+2
* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-0/+2
* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-221-0/+3
* std_names: add *_reduce names.Tristan Gingold2020-03-131-0/+6
* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-0/+1
* [PATCH] Add names for synopsys packages.Tristan Gingold2020-03-031-8/+10
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-0/+4
* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-0/+1
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-3/+3
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-0/+1
* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-261-0/+2
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-041-5/+6
* Add names for formal input gates/attributes.Tristan Gingold2019-10-301-0/+5
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-111-0/+2
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-111-1/+1
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-101-0/+1
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-071-0/+1
* vhdl: recognize rotate functions.Tristan Gingold2019-09-221-0/+2
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-111-0/+2
* std_names: add std_matchTristan Gingold2019-08-301-0/+1
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-161-3/+3
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-141-22/+22
* vhdl: handle (discard) more pragmas.Tristan Gingold2019-07-251-0/+5
* vhdl scanner: handle pragma translate_on/translate_off.Tristan Gingold2019-07-241-0/+3
* vhdl: recognize resize function.Tristan Gingold2019-07-241-0/+1
* std_names: add names for math_real.Tristan Gingold2019-06-281-0/+3
* vhdl: recognize to_integer/to_signed/to_unsigned.Tristan Gingold2019-06-201-0/+3
* names: add more sv names.Tristan Gingold2019-05-111-1/+21
* std_names: remove duplicate entries.Tristan Gingold2018-12-171-10/+0
* std_names: add new names.Tristan Gingold2018-12-071-3/+24
* std_names: add identifiers from EDIF.Tristan Gingold2018-11-141-2/+33
* reorder names.Tristan Gingold2018-08-041-105/+216
* rework parse_expression to add parse_binary_expression.Tristan Gingold2018-08-041-6/+6
* std_names: add more keywords.Tristan Gingold2018-02-081-2/+6
* std_names: add localparam, trior, triand..Tristan Gingold2018-02-061-0/+4
* libraries: get rid of Nam_Buffer.Tristan Gingold2018-01-201-0/+1
* Preliminary support for tool directives.Tristan Gingold2017-11-061-0/+5
* textio: use grt.fcvt to write reals.Tristan Gingold2017-04-191-0/+1
* textio: use grt.fcvt to read real numbers.Tristan Gingold2017-04-191-0/+1
* vhdl08: implement 'subtype attributeTristan Gingold2017-01-131-0/+2
* ieee: recognize ieee.numeric_std.Tristan Gingold2016-12-301-0/+6
* name_table: auto-initialize.Tristan Gingold2016-11-011-2/+0
* vhdl08: parse parameter reserved word.Tristan Gingold2016-09-251-1/+1
* Display a nice message if std_logic_textio is not found.Tristan Gingold2016-08-271-0/+1