iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: decode to_x01 (from ieee.std_logic_1164)	Tristan Gingold	2020-06-19	1	-18/+21
*	vhdl: recognize math_real.floor. For #1210	Tristan Gingold	2020-04-11	1	-6/+7
*	vhdl: handle pragma synthesis_on/synthesis_off.	Tristan Gingold	2020-04-11	1	-1/+3
*	vhdl: recognize ext/sxt from std_logic_arith.	Tristan Gingold	2020-04-11	1	-1/+3
*	synth: handle ieee.numeric_std.to_01	Tristan Gingold	2020-03-22	1	-16/+19
*	std_names: add *_reduce names.	Tristan Gingold	2020-03-13	1	-5/+11
*	vhdl-ieee-std_logic_arith: recognize more conversions.	Tristan Gingold	2020-03-11	1	-5/+6
*	[PATCH] Add names for synopsys packages.	Tristan Gingold	2020-03-03	1	-47/+51
*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	1	-11/+15
*	synth: handle ieee.math_real.round Fix #1075	Tristan Gingold	2020-01-10	1	-3/+4
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	1	-3/+3
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	1	-8/+9
*	vhdl: recognize sin and cos from math_real.	Tristan Gingold	2019-11-26	1	-1/+3
*	vhdl-scanner: handle 'synopsys' pragma.	Tristan Gingold	2019-11-04	1	-10/+11
*	Add names for formal input gates/attributes.	Tristan Gingold	2019-10-30	1	-1/+8
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-4/+6
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-2/+2
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	1	-3/+4
*	vhdl: recognize to_bitvector.	Tristan Gingold	2019-10-07	1	-3/+4
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	1	-3/+5
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	1	-3/+5
*	std_names: add std_match	Tristan Gingold	2019-08-30	1	-3/+4
*	vhdl: recognize PSL units reserved words.	Tristan Gingold	2019-08-16	1	-10/+10
*	vhdl: add PSL keywords to vhdl08 reserved words.	Tristan Gingold	2019-08-14	1	-133/+135
*	vhdl: handle (discard) more pragmas.	Tristan Gingold	2019-07-25	1	-1/+6
*	vhdl scanner: handle pragma translate_on/translate_off.	Tristan Gingold	2019-07-24	1	-1/+4
*	vhdl: recognize resize function.	Tristan Gingold	2019-07-24	1	-3/+4
*	std_names: add names for math_real.	Tristan Gingold	2019-06-28	1	-1/+4
*	vhdl: recognize to_integer/to_signed/to_unsigned.	Tristan Gingold	2019-06-20	1	-1/+4
*	names: add more sv names.	Tristan Gingold	2019-05-11	1	-39/+60
*	std_names: add new names.	Tristan Gingold	2018-12-07	1	-5/+16
*	std_names: add identifiers from EDIF.	Tristan Gingold	2018-11-14	1	-18/+50
*	reorder names.	Tristan Gingold	2018-08-04	1	-330/+458
*	rework parse_expression to add parse_binary_expression.	Tristan Gingold	2018-08-04	1	-101/+102
*	std_names: add more keywords.	Tristan Gingold	2018-02-08	1	-10/+13
*	std_names: add localparam, trior, triand..	Tristan Gingold	2018-02-06	1	-7/+14
*	libraries: get rid of Nam_Buffer.	Tristan Gingold	2018-01-20	1	-16/+17
*	Preliminary support for tool directives.	Tristan Gingold	2017-11-06	1	-1/+6
*	Name_Last_Character: use usual notation.	Tristan Gingold	2017-10-05	1	-3/+2
*	textio: use grt.fcvt to write reals.	Tristan Gingold	2017-04-19	1	-2/+3
*	textio: use grt.fcvt to read real numbers.	Tristan Gingold	2017-04-19	1	-2/+3
*	vhdl08: implement 'subtype attribute	Tristan Gingold	2017-01-13	1	-4/+10
*	ieee: recognize ieee.numeric_std.	Tristan Gingold	2016-12-30	1	-4/+10
*	vhdl08: parse parameter reserved word.	Tristan Gingold	2016-09-25	1	-40/+40
*	Display a nice message if std_logic_textio is not found.	Tristan Gingold	2016-08-27	1	-1/+2
*	Improve error message if synopsys package it not found.	Tristan Gingold	2016-07-18	1	-13/+16
*	Add context declaration and reference (vhdl 2008).	Tristan Gingold	2015-05-12	1	-13/+20
*	Move sources to src/ subdirectory.	Tristan Gingold	2014-11-04	1	-0/+727