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* update license headersumarcor2021-02-051-5/+3
* synth: fix handling of multi-dim ROM. Fix #1390Tristan Gingold2020-07-241-16/+13
* netlists-memories: minor style fix.Tristan Gingold2020-07-221-2/+2
* netlists-memories: simplify addresses when using a 'to' range. Fix #1348Tristan Gingold2020-06-021-0/+264
* netlists-memories: clean up: remove handling of dff/idff in chains.Tristan Gingold2020-06-021-57/+28
* netlists-memories: handle another merge of dff in read ports. For #1348Tristan Gingold2020-06-021-3/+154
* synth: improve support of true dual port rams. For #1069Tristan Gingold2020-05-311-4/+5
* netlists-memories: cleanup.Tristan Gingold2020-05-291-41/+4
* netlists: rework clock handling in memories.Tristan Gingold2020-05-291-65/+82
* netlists: handle UL32 in memory initial value.Tristan Gingold2020-05-291-3/+16
* netlists: complete support of attributes. For #1318Tristan Gingold2020-05-231-0/+1
* netlists-memories: set location on utrunc. Fix #1332Tristan Gingold2020-05-211-1/+1
* synth: improve handling of synchronous memory read.Tristan Gingold2020-04-281-6/+92
* synth: add many calls to set_locationTristan Gingold2020-04-261-0/+5
* netlists-memories: Handle gated dyn_extract.Tristan Gingold2020-04-261-25/+236
* netlists-memories: improve support of memoriesTristan Gingold2020-04-221-46/+50
* synth: handle multi-dim ROMS. Fix #1220Tristan Gingold2020-04-131-14/+33
* netlists-memories: handle (some) slices of ROM outputs. Fix #1219Tristan Gingold2020-04-131-18/+48
* synth: improve output of memory initial value.Tristan Gingold2020-03-291-3/+8
* netlists-memories: add flag_memory_verboseTristan Gingold2020-03-281-2/+7
* synth: remove useless note message.Tristan Gingold2020-03-281-2/+5
* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-281-321/+542
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-19/+45
* netlists-memories: also reduce muxes for extract.Tristan Gingold2020-02-211-7/+35
* netlists-memories: factorize code.Tristan Gingold2020-02-201-235/+191
* synthesis: rework memory inference.Tristan Gingold2020-02-161-22/+90
* netlists-memories: handle split memories. Fix #1127Tristan Gingold2020-02-111-8/+18
* netlists-memories: cleanup.Tristan Gingold2020-02-101-319/+1
* synth: rework (again) memory inference.Tristan Gingold2020-02-101-38/+237
* synth: fix a typo in a comment.Tristan Gingold2020-01-181-1/+1
* netlists-memories: fix split of memory content. FixTristan Gingold2020-01-161-4/+131
* netlists-memories: allow initialized rams. For #1090Tristan Gingold2020-01-131-1/+2
* netlists-memories: allow intermediate signals to detect sync read.Tristan Gingold2020-01-121-2/+2
* netlists-disp_vhdl: handle conversion from std_logic to signed/unsigned.Tristan Gingold2019-12-241-6/+8
* netlists-memories: add convert_to_memory.Tristan Gingold2019-12-241-298/+504
* synth: add Get_Input_Instance.Tristan Gingold2019-12-141-10/+8
* netlists-memories: add comments.Tristan Gingold2019-12-141-2/+44
* netlists-memories: remove unused subprograms.Tristan Gingold2019-12-081-318/+0
* netlists-memories: reduce muxes.Tristan Gingold2019-12-081-1/+162
* synth: rework in netlists-memories.Tristan Gingold2019-12-061-61/+128
* netlists-memories: avoid a crash when no read. Fix #1018Tristan Gingold2019-12-051-1/+7
* netlists-memories: improve ROM inference. For issue #1008Tristan Gingold2019-12-051-26/+48
* netlists-memories: generate mem_rd_sync gates.Tristan Gingold2019-12-051-169/+142
* netlists-memories: rework.Tristan Gingold2019-12-051-2/+855
* netlists-memories: do not crash on anonymous ROM.Tristan Gingold2019-11-121-3/+6
* netlists: optimize trunc.Tristan Gingold2019-11-111-1/+3
* netlists-memories: truncate wide addresses.Tristan Gingold2019-11-051-11/+9
* netlists-memories: adjust message.Tristan Gingold2019-11-051-1/+1
* synth: fix multiport read memories (for issue #1000)Tristan Gingold2019-11-031-1/+3
* netlits: fix memidx order.Tristan Gingold2019-11-011-1/+3
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