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* synth: handle package bodies.Tristan Gingold2019-10-071-0/+4
* synth: renaming and minor refactoring.Tristan Gingold2019-09-301-9/+9
* synth: special handling of 'const' functions.Tristan Gingold2019-09-301-0/+5
* synth: do not create self-instance on black-boxed modules.Tristan Gingold2019-09-211-1/+3
* synth: add bit0/bit1 in instance.Tristan Gingold2019-09-211-0/+6
* synth: add Get_Build (WIP).Tristan Gingold2019-09-201-0/+4
* synth: add base_instance.Tristan Gingold2019-09-201-2/+14
* synth: rename get/set_module for instances.Tristan Gingold2019-09-201-3/+3
* synth-context: get rid off Set_Block_Scope.Tristan Gingold2019-09-201-4/+1
* synth-context: make Objects_Array private.Tristan Gingold2019-09-201-1/+2
* synth: refactoring to reduce global variables.Tristan Gingold2019-09-191-4/+2
* synth: synth_instance_type is now limited.Tristan Gingold2019-09-191-6/+2
* synth: make synth_instance_type private.Tristan Gingold2019-09-191-21/+41
* synth: improve support of return statement.Tristan Gingold2019-09-111-2/+0
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-281-1/+4
* synth: make type Wire_Id_Record private.Tristan Gingold2019-07-171-2/+0
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-0/+2
* synth: handle simple user function calls.Tristan Gingold2019-07-061-0/+2
* synth: destroy iterator after for-loop.Tristan Gingold2019-07-011-0/+3
* vhdl: move annotations from simul to vhdl.Tristan Gingold2019-06-291-1/+1
* synth: get rid of execution and elaboration.Tristan Gingold2019-06-191-10/+28
* synth: add comments.Tristan Gingold2019-06-071-2/+7
* synth: add comments and refactoring.Tristan Gingold2019-06-071-0/+21
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-1/+1
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-241-1/+1
* simulation: refactoring (move block_instance to iir_values).Tristan Gingold2017-11-241-1/+1
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+50