| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: move ieee packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -13/+13 |
| * | vhdl: move std_standard package to vhdl child. | Tristan Gingold | 2019-05-05 | 1 | -3/+3 |
| * | synth: improve generation of aggregates. | Tristan Gingold | 2019-04-16 | 1 | -13/+61 |
| * | synth: minimal support of slices. | Tristan Gingold | 2019-04-16 | 1 | -0/+87 |
| * | synth-expr: handle others in aggregate. | Tristan Gingold | 2019-04-16 | 1 | -0/+5 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -3/+3 |
| * | Update simulate. | Tristan Gingold | 2017-11-08 | 1 | -1/+1 |
| * | synth: support nand, nor, xnor. | Tristan Gingold | 2017-02-26 | 1 | -0/+12 |
| * | synth: reverse bit order for indexed names. | Tristan Gingold | 2017-02-16 | 1 | -2/+2 |
| * | synth: Fix handling of iir_downto in synth_indexed_name. | Tristan Gingold | 2017-02-15 | 1 | -1/+1 |
| * | synth-expr.adb: fix Synth_Indexed_Name. | Tristan Gingold | 2017-02-13 | 1 | -2/+2 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+726 |
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index : iCE40/ghdl | |
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