iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	synth-vhdl_expr: do not abort on array subtype conversion	Tristan Gingold	2022-06-04	1	-0/+3
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	1	-1/+1
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*	synth-vhdl_oper: add hook for falling edge, handle aliases.	Tristan Gingold	2022-05-29	1	-3/+8
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*	elab-vhdl_objtypes: use value_offsets for record elements offset.	Tristan Gingold	2022-05-24	1	-6/+7
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*	synth: use same elements for unbounded arrays and vectors	Tristan Gingold	2022-05-22	1	-2/+3
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*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	1	-1/+1
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*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-345/+103
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*	synth-vhdl_expr: avoid a memocy copy	Tristan Gingold	2022-05-21	1	-3/+7
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*	synth-vhdl_expr: add an hook to get the value of a signal	Tristan Gingold	2022-05-12	1	-0/+3
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*	synth: avoid a crash after an error	Tristan Gingold	2022-04-29	1	-0/+15
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*	synth: do not add info for element subtype (except for arrays).	Tristan Gingold	2022-04-05	1	-1/+2
\| \| \| \|	Fix #2021
*	synth-vhdl_expr: minor refactoring - add comments	Tristan Gingold	2022-03-20	1	-16/+34
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*	synth-vhdl_expr(value2logvec): fix vlen handling. Fix #2013	Tristan Gingold	2022-03-20	1	-7/+13
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*	synth: handle concatenation of unbounded types. Fix #1993	Tristan Gingold	2022-03-08	1	-44/+0
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*	synth: properly propagate bound errors. Fix #1972	Tristan Gingold	2022-02-17	1	-11/+28
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*	synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920	Tristan Gingold	2021-11-21	1	-0/+7
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*	synth: Support alias declarations in vunit	tmeissner	2021-11-02	1	-1/+3
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*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-236/+48
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*	synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886	Tristan Gingold	2021-10-10	1	-42/+74
\| \| \| \|	And add comments
*	synth-vhdl_expr: fix handling of negative factor in slice. For #1886	Tristan Gingold	2021-10-09	1	-25/+61
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*	synth: improve result of is_positive	Tristan Gingold	2021-08-29	1	-3/+5
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*	vhdl: remove iir_kind_anonymous_signal_declaration (now unused)	Tristan Gingold	2021-08-24	1	-3/+0
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*	synth-vhdl_expr: adjust width of memidx for indexed names.	Tristan Gingold	2021-06-21	1	-1/+1
\| \| \| \|	In general the width of memidx is ignored, but it's better to correctly set it
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-0/+2572