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path: root/src/synth/synth-vhdl_oper.adb
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* synth: handle bit reduction operators. Fix #2328Tristan Gingold2023-01-291-7/+14
* synth-vhdl_oper: add bit-vect and vect-bit operations.Tristan Gingold2023-01-271-12/+24
* synth: rework error handling in file operationsTristan Gingold2023-01-111-1/+1
* synth: fix memory allocation in predefined function callsTristan Gingold2023-01-101-0/+3
* synth: handle indexes in arrays conversionTristan Gingold2023-01-101-1/+1
* synth: add support for numeric_std_unsigned add, sub, fix #2286tmeissner2022-12-261-2/+8
* synth: add support for to_x01z. Fix #2285Tristan Gingold2022-12-261-1/+3
* synth-vhdl_oper: handle more operators.Tristan Gingold2022-11-301-51/+131
* synth-vhdl_oper: complete rework on predefined functions.Tristan Gingold2022-11-301-644/+570
* synth-vhdl_oper: refactoringTristan Gingold2022-11-301-61/+86
* synth-vhdl_eval(eval_static_predefined_function_call): handle all operationsTristan Gingold2022-11-281-33/+35
* synth: handle bit/unsigned and bit/signed vhdl 08 operators.Tristan Gingold2022-11-021-12/+36
* synth: internal refactoringTristan Gingold2022-10-291-8/+23
* synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_miscTristan Gingold2022-10-191-16/+34
* synth-vhdl_oper: handle and_reduce. Fix #2224Tristan Gingold2022-10-191-1/+10
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-251-20/+34
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-181-1/+1
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-111-4/+8
* synth: use areapoolsTristan Gingold2022-09-021-4/+13
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-7/+9
* synth-vhdl_oper.adb: fix mul uns uns. Fix #2169Tristan Gingold2022-08-101-1/+1
* synth-vhdl_oper: remove check for positive rotation amount. Fix #2159Tristan Gingold2022-08-041-3/+1
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-111-2/+2
* synth-vhdl_oper: handle more bit_vector operations. Fix #2074Tristan Gingold2022-06-051-8/+13
* synth-vhdl_oper: add hooks for bit edgeTristan Gingold2022-05-301-0/+12
* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-301-18/+21
* synth-vhdl_oper: add hook for falling edge, handle aliases.Tristan Gingold2022-05-291-0/+4
* synth-vhdl_oper: add an hook for rising_edgeTristan Gingold2022-05-231-0/+4
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-221-3/+3
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-16/+16
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-4/+4
* synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062Tristan Gingold2022-05-171-0/+1
* synth: renaming (synth-static_oper -> synth-vhdl_eval)Tristan Gingold2022-04-271-4/+4
* synth: abstract code for reuse by evaluationTristan Gingold2022-04-261-1/+1
* synth-static_oper: fully remove dependency on synth_instanceTristan Gingold2022-04-261-8/+35
* synth-static_oper: do not depend on instance for static operations.Tristan Gingold2022-04-261-29/+5
* synth: handle concatenation of unbounded types. Fix #1993Tristan Gingold2022-03-081-8/+25
* synth-vhdl_oper: implement <= for arrays. Fix #1991Tristan Gingold2022-03-021-7/+17
* synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977Tristan Gingold2022-02-171-27/+30
* synth-vhdl_oper: handle bit condition operator. Fix #1971Tristan Gingold2022-02-161-1/+2
* synth: fix handling of std_logic_unsigned."-" for negative numbers.Tristan Gingold2022-01-181-8/+12
* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-1/+4
* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-281-4/+4
* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-281-2/+2
* synth-vhdl_oper.adb: handle resize uns/uns. For #1731Tristan Gingold2021-04-211-0/+12
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