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* synth: rework association conversionsTristan Gingold2022-09-251-28/+59
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-251-106/+236
* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-191-41/+81
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-181-5/+5
* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
* synth: handle incomplete typesTristan Gingold2022-09-171-10/+11
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-31/+49
* synth: improve handling of complex typesTristan Gingold2022-09-151-1/+1
* synth: handle vhdl-87 filesTristan Gingold2022-09-151-0/+6
* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-121-1/+3
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-111-3/+4
* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-45/+136
* simul: add support for protected objectsTristan Gingold2022-09-081-10/+75
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-2/+2
* synth-vhdl_stmts: fix handling of copyback parametersTristan Gingold2022-09-071-6/+19
* simul: add an hook to display report/assert messageTristan Gingold2022-09-061-32/+68
* synth: use areapoolsTristan Gingold2022-09-021-14/+70
* synth: factorize code for tracing statements executionTristan Gingold2022-09-021-13/+2
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-9/+8
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-201-20/+16
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-191-6/+30
* synth: handle assignment to record aggregateTristan Gingold2022-08-141-29/+102
* synth-vhdl_expr: add support for branch quantitiesTristan Gingold2022-07-281-0/+1
* synth: add hook for dot attributeTristan Gingold2022-07-241-2/+5
* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-111-1/+1
* synth-vhdl_stmts: fix handling of instantiated subprogramsTristan Gingold2022-06-061-1/+3
* synth-vhdl_stmts: handle alias in assignment expressionTristan Gingold2022-06-061-2/+1
* synth-vhdl_stmts: do not convert out variable on callTristan Gingold2022-05-311-3/+8
* synth-vhdl_stmts: export Synth_Subprogram_Back_AssociationTristan Gingold2022-05-311-7/+10
* synth-vhdl_stmts: export two procedures, adjust assertion messageTristan Gingold2022-05-291-5/+6
* synth: move procedure call copyback values in contextTristan Gingold2022-05-251-69/+25
* vhdl: move Is_Copyback_Parameter to vhdl-utilsTristan Gingold2022-05-251-12/+2
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-251-66/+125
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-241-4/+1
* synth-vhdl_stmts: minor refactoringTristan Gingold2022-05-241-12/+23
* synth-vhdl_stmts: rework synth_subprogram_associationTristan Gingold2022-05-231-35/+35
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-221-4/+4
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-2/+2
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-2/+4
* synth-vhdl_stmts: write generic procedure Assign_Aggregate.Tristan Gingold2022-05-211-14/+16
* synth-vhdl_stmts: avoid a crash after an error. Fix #2063Tristan Gingold2022-05-181-1/+4
* synth-vhdl_stmts: add comments about report statementsTristan Gingold2022-05-181-5/+51
* synth-vhdl_stmts: add a commentTristan Gingold2022-05-171-0/+2
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