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* synth-vhdl_eval: minor refactoringTristan Gingold2022-11-301-32/+38
* synth-vhdl_oper: handle more operators.Tristan Gingold2022-11-301-51/+131
* synth-vhdl_oper: complete rework on predefined functions.Tristan Gingold2022-11-302-645/+571
* synth-vhdl_oper: refactoringTristan Gingold2022-11-301-61/+86
* synth-vhdl_eval(eval_static_predefined_function_call): handle all operationsTristan Gingold2022-11-283-983/+953
* synth: improve error message for ghdl/ghdl-yosys-plugin#179Tristan Gingold2022-11-151-1/+3
* synth: avoid a crash on signal assignment in non-sensitized process.Tristan Gingold2022-11-141-2/+9
* Remove trailing spacesTristan Gingold2022-11-081-1/+1
* elab-vhdl_expr: fix a crash on simple aggregates. Fix #2240Tristan Gingold2022-11-082-15/+13
* Added id to warnings related to attributes. (#2242)cderrien2022-11-084-2/+20
* Escape port name in dot output. (#2241)cderrien2022-11-081-1/+1
* netlists-memories: refactoringTristan Gingold2022-11-061-113/+105
* netlists-memories: factorize code.Tristan Gingold2022-11-061-83/+41
* netlists: factorize codeTristan Gingold2022-11-061-100/+56
* synth-environment.adb: fix warningTristan Gingold2022-11-051-1/+0
* synth: rework memory inference. Fix #2232Tristan Gingold2022-11-053-78/+233
* netlists-builders: allow building mem_wr_sync without clk and en.Tristan Gingold2022-11-051-4/+10
* synth: infere a dff (instead of an idff) when the init value is XTristan Gingold2022-11-032-6/+21
* synth: handle bit/unsigned and bit/signed vhdl 08 operators.Tristan Gingold2022-11-021-12/+36
* netlists-inference: handle flip-flop with different patterns.Tristan Gingold2022-10-301-23/+75
* netlists-gates: add a commentTristan Gingold2022-10-301-0/+1
* synth: internal refactoringTristan Gingold2022-10-294-121/+93
* elab-vhdl_types: abstract elab_floating_type_definitionTristan Gingold2022-10-291-10/+15
* synth: fix crash in disp_verilog. Fix #2234Tristan Gingold2022-10-291-3/+8
* synth: handle copyback associations in any order.Tristan Gingold2022-10-191-12/+30
* synth-vhdl_eval: handle std_logic_misc reduce functionsTristan Gingold2022-10-191-0/+27
* synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_miscTristan Gingold2022-10-191-16/+34
* synth-vhdl_oper: handle and_reduce. Fix #2224Tristan Gingold2022-10-191-1/+10
* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-183-142/+241
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
* synth: avoid extra conversion during alias elaborationTristan Gingold2022-10-141-6/+4
* synth: handle alias of access objects.Tristan Gingold2022-10-131-1/+1
* simul: handle last_event and last_activeTristan Gingold2022-10-132-0/+16
* elab-vhd_expr: handle more cases in exec_type_of_objectTristan Gingold2022-10-131-1/+4
* synth-vhdl_stmts(synth_verification_unit): always set instance_pool.Tristan Gingold2022-10-131-1/+3
* synth: fix crashes on scalar attribute with anonymous subtype.Tristan Gingold2022-10-101-2/+2
* simul: signal attributes in actualsTristan Gingold2022-10-061-2/+4
* simul: complete concurrent procedure callsTristan Gingold2022-10-062-2/+5
* simul: improve debugger (display of signals value)Tristan Gingold2022-10-063-11/+48
* elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205Tristan Gingold2022-10-041-2/+4
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-033-17/+46
* synth: improve error recoveryTristan Gingold2022-10-021-0/+3
* synth: detect division by 0, handle universal real/integer divisionTristan Gingold2022-10-021-3/+23
* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
* synth: avoid a crash on literal overflowTristan Gingold2022-10-011-1/+10
* synth: avoid on crash on overflow in rangesTristan Gingold2022-10-011-0/+8
* synth: improve handling of individual generic associationsTristan Gingold2022-10-011-17/+22
* simul: finalize declarations of procedure callsTristan Gingold2022-10-011-0/+2
* synth: handle read for floatsTristan Gingold2022-09-301-0/+12
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