aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl/vhdl-nodes.adb
Commit message (Expand)AuthorAgeFilesLines
* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-101-0/+16
* vhdl: add an owner to interface type definitionTristan Gingold2022-08-071-0/+16
* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-071-0/+32
* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-291-0/+16
* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-251-0/+16
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-17/+17
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-161-1/+1
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-121-0/+16
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-1/+33
* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-0/+2
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-041-0/+16
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-5/+6
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-16/+17
* Add parsing of case? statement and simple test.Brian Padalino2021-09-241-0/+16
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-0/+16
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-1/+0
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-0/+1
* vhdl-nodes: do not reset free hooks on initializationTristan Gingold2021-06-261-1/+0
* vhdl-nodes: Initialize global state to allow restart.Tristan Gingold2021-06-191-0/+2
* vhdl: remove unused Get/Set_Alias_DeclarationTristan Gingold2021-05-161-16/+0
* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+17
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+2
* update license headersumarcor2021-01-141-11/+9
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-0/+32
* Rework initialization and finalization.Tristan Gingold2020-12-301-1/+5
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-0/+16
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-2/+2
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+18
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+39
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-9/+8
* vhdl-nodes: reduce size of Iterator_Declaration.Tristan Gingold2020-07-011-3/+3
* vhdl-nodes: add Open_Flag to all generic interfaces.Tristan Gingold2020-06-261-2/+2
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-4/+20
* Synthesis of PSL prev function.Tristan Gingold2020-06-021-8/+8
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-0/+52
* vhdl-nodes: use a flag field for direction.Tristan Gingold2020-05-201-2/+7
* vhdl: allow attribute specifications in protected types. For #1252Tristan Gingold2020-04-201-22/+22
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-4/+4
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-0/+35
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+16
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+1
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-1/+36
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+2
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-0/+16
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-13/+391
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+16
* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+32
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-9/+9
* synth: handle verification units.Tristan Gingold2019-08-201-1/+17
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-2/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 11:37:48 +0000