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* vhdl/translate: elaborate dependencies of configurations. Fix #984Tristan Gingold2019-10-241-0/+4
* synth: add support for declarations in vunits.Tristan Gingold2019-10-232-4/+27
* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
* vhdl-annotations: handle some declarations in vunits.Tristan Gingold2019-10-231-0/+6
* vhdl-canon: handle some declarations in vunits.Tristan Gingold2019-10-231-2/+18
* vhdl-sem_psl: analyze some declarations.Tristan Gingold2019-10-231-0/+18
* vhdl-sem_decls: make sem_declaration public.Tristan Gingold2019-10-235-14/+31
* vhdl-sem_decls: extract sem_declaration.Tristan Gingold2019-10-231-121/+118
* netlists-dump: dump input net width.Tristan Gingold2019-10-231-0/+2
* vhdl-sem_decls: add comment.Tristan Gingold2019-10-211-0/+3
* vhdl-parse: parse declarations in vunit.Tristan Gingold2019-10-211-327/+352
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-211-0/+1
* vhdl: handle labels in verification units.Tristan Gingold2019-10-211-8/+62
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-215-84/+103
* psl: add active state.Tristan Gingold2019-10-215-20/+78
* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
* psl-nfas-utils: reuse True_Node.Tristan Gingold2019-10-211-4/+2
* nelists-memories: reject memories with reset.Tristan Gingold2019-10-211-1/+4
* synth-stmts: set location of muxes on case statements.Tristan Gingold2019-10-211-6/+13
* synth: fixes for value_const.Tristan Gingold2019-10-202-0/+11
* vhdl: try to convert identifier to token only for identifiersTristan Gingold2019-10-201-1/+3
* netlists-memories: fixes in ROM.Tristan Gingold2019-10-201-48/+51
* netlists-disp_vhdl: display memory initialization value.Tristan Gingold2019-10-201-2/+46
* synth: add value_const.Tristan Gingold2019-10-207-9/+69
* netlists-memories: preliminary work to handle ROM.Tristan Gingold2019-10-201-111/+194
* synth: add more locations.Tristan Gingold2019-10-202-0/+2
* netlists-dump: also dump instances location.Tristan Gingold2019-10-201-6/+34
* synth: use note messages for memories (instead of warnings).Tristan Gingold2019-10-194-28/+34
* ghdlsynth.h: add functions.Tristan Gingold2019-10-191-0/+4
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-181-0/+5
* netlists-memories: check ports.Tristan Gingold2019-10-181-7/+161
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
* synth-stmts: ignore EOS in PSL expressions.Tristan Gingold2019-10-181-1/+8
* syn_interning: add get_index.Tristan Gingold2019-10-172-14/+31
* netlists-disp_vhdl: display memories.Tristan Gingold2019-10-171-1/+97
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-178-18/+553
* netlists: add remove_instance.Tristan Gingold2019-10-162-0/+35
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-164-11/+65
* synth: fix psl cover - test when the final state is reached.Tristan Gingold2019-10-151-3/+14
* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-153-0/+37
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-155-1/+17
* synth: handle overflow literal.Tristan Gingold2019-10-152-1/+9
* netlists: declare memory gates.Tristan Gingold2019-10-153-3/+215
* synth-expr: handle any discrete_range in aggregate choices.Tristan Gingold2019-10-151-1/+2
* synth-insts: accept architecture instantiation in synth_dependencies.Tristan Gingold2019-10-151-2/+3
* Use Decode_Work_Option in options. Factorize code.Tristan Gingold2019-10-154-25/+11
* ghdlsynth: allow --work= option in the middle of files.Tristan Gingold2019-10-153-1/+48
* synth-inference: handle multiple connections.Tristan Gingold2019-10-141-14/+31
* synth-infere: extract clock from and tree.Tristan Gingold2019-10-141-17/+102
* netlists-dump: do not print name of anonymous parameters.Tristan Gingold2019-10-141-2/+6
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