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* synth: adjustments for foreign_moduleTristan Gingold2021-11-282-3/+12
* synth: add a hook to resolve foreign instantiation namesTristan Gingold2021-11-282-0/+8
* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
* vhdl-parse: improve error message for empty recordsTristan Gingold2021-11-281-29/+33
* vhdl/translate: handle target aggregate with unbounded names. Fix #1914Tristan Gingold2021-11-244-22/+75
* vhdl-sem_decls: avoid a crash on invalid alias name. Fix #1919Tristan Gingold2021-11-211-0/+10
* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
* synth: put direction into port descTristan Gingold2021-11-178-31/+30
* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
* synth: add ports attributesTristan Gingold2021-11-173-0/+120
* vhdl-utils.adb: minor refactoringTristan Gingold2021-11-171-7/+3
* grt: refactoring to fix build failure. For #1913Tristan Gingold2021-11-175-394/+443
* Add commentsTristan Gingold2021-11-172-0/+4
* vhdl-evaluation: use grt to compute value attribute for integers.Tristan Gingold2021-11-173-33/+97
* grt/Makefile.inc: add a dependency for grt-cgnatrts.Tristan Gingold2021-11-161-2/+3
* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
* vhdl-evaluation: catch bad parameter for value attribute. Fix #1913Tristan Gingold2021-11-151-1/+7
* vhdl-sem_expr: improve code generation for multi-dim aggregatesTristan Gingold2021-11-151-3/+3
* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
* std_names: add syn_black_boxTristan Gingold2021-11-122-1/+3
* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-112-4/+20
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-0923-662/+730
* lists: add a subtype for valid listsTristan Gingold2021-11-092-2/+4
* ghdlcomp: exit with error status in case of error. For #1908Tristan Gingold2021-11-051-0/+4
* vhdl-configuration: stop earlier in case of error. Fix #1908Tristan Gingold2021-11-051-17/+19
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-058-64/+143
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-049-362/+422
* vhdl: add tok_inherit. Preliminary work for #1899Tristan Gingold2021-11-035-21/+27
* trans-chap7: convert to base type for array-element operation. For #1898Tristan Gingold2021-11-031-3/+5
* synth: Support alias declarations in vunittmeissner2021-11-026-8/+23
* synth: do full elaboration before synthesisTristan Gingold2021-11-0161-2038/+5349
* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-015-219/+256
* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
* vhdl-configuration.adb: avoid a crash in case of error. Fix #1897Tristan Gingold2021-10-181-2/+11
* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
* ortho/debug and ortho/oread: also increase identifier buffers. For #1894Tristan Gingold2021-10-182-2/+2
* trans.adb: increased maximum identifier length. Fix #1894Tristan Gingold2021-10-161-1/+1
* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-135-4/+12
* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
* vhdl-scanner: improve error message. Fix #1883Tristan Gingold2021-10-061-1/+2
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