iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
...
*	synth: add base_instance.	Tristan Gingold	2019-09-20	4	-23/+55
\|
*	synth: rename get/set_module for instances.	Tristan Gingold	2019-09-20	5	-25/+23
\|
*	synth-context: get rid off Set_Block_Scope.	Tristan Gingold	2019-09-20	6	-35/+24
\|
*	synth-context: make Objects_Array private.	Tristan Gingold	2019-09-20	1	-1/+2
\|
*	interning: now based on dyn_interning.	Tristan Gingold	2019-09-20	2	-106/+25
\|
*	synth: refactoring to reduce global variables.	Tristan Gingold	2019-09-19	6	-28/+46
\|
*	synth: synth_instance_type is now limited.	Tristan Gingold	2019-09-19	1	-6/+2
\|
*	synth: make synth_instance_type private.	Tristan Gingold	2019-09-19	7	-81/+160
\|
*	synth: handle unconnected out ports.	Tristan Gingold	2019-09-19	1	-5/+8
\|
*	synth: handle record subtypes.	Tristan Gingold	2019-09-19	3	-42/+59
\|
*	synth: Add support for PSL cover directive (#930)	T. Meissner	2019-09-19	6	-3/+49
\| \| \| \| \| \|	* synth: Add support for PSL cover directive * testsuite/synth: Add tests for PSL cover directives
*	synth: improve locations tracking.	Tristan Gingold	2019-09-18	8	-7/+84
\|
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	5	-63/+173
\|
*	synth: remove value_mux2.	Tristan Gingold	2019-09-18	5	-55/+32
\|
*	synth: fix to get_current_assign_value.	Tristan Gingold	2019-09-17	1	-7/+4
\|
*	netlists-dump: add width on extract output.	Tristan Gingold	2019-09-17	1	-5/+14
\|
*	synth: add debug flag -dc to not clean.	Tristan Gingold	2019-09-17	3	-1/+9
\|
*	synth-inference: detect false loop.	Tristan Gingold	2019-09-17	6	-2/+335
\|
*	synth: fold addition on constant nets.	Tristan Gingold	2019-09-17	10	-49/+178
\|
*	synth: add synth-flags, add debug option -di.	Tristan Gingold	2019-09-17	3	-1/+32
\|
*	synth: minor refactoring about const gates.	Tristan Gingold	2019-09-15	4	-40/+41
\|
*	synth-oper: add support of std_match	Tristan Gingold	2019-09-15	1	-0/+94
\|
*	synth-disp_vhdl: improve support of boolean, suv.	Tristan Gingold	2019-09-15	1	-17/+16
\|
*	synth: add build2_const_vec	Tristan Gingold	2019-09-15	2	-0/+27
\|
*	synth-stmts: fix uninitialized variable.	Tristan Gingold	2019-09-13	1	-1/+9
\|
*	synth: initialize subprogram variables.	Tristan Gingold	2019-09-13	4	-8/+14
\|
*	synth: remove get_width from synth-expr	Tristan Gingold	2019-09-12	3	-15/+2
\|
*	synth: extract synth-oper from synth-expr	Tristan Gingold	2019-09-12	6	-927/+1012
\|
*	synth: handle simple_aggregate.	Tristan Gingold	2019-09-12	1	-0/+41
\|
*	synth: allow empty string literal.	Tristan Gingold	2019-09-12	2	-2/+4
\|
*	vhdl-nodes: add a comment.	Tristan Gingold	2019-09-12	1	-1/+1
\|
*	synth: handle unsigned shift right	Tristan Gingold	2019-09-11	1	-0/+7
\|
*	vhdl-ieee-numeric: recognize shift_right.	Tristan Gingold	2019-09-11	1	-17/+31
\|
*	synth: handle unsigned shift left.	Tristan Gingold	2019-09-11	5	-107/+163
\|
*	synth: add synth_compare_sgn_sgn	Tristan Gingold	2019-09-11	1	-0/+23
\|
*	synth: handle constant bit compare.	Tristan Gingold	2019-09-11	1	-0/+6
\|
*	synth: handle numeric_std.resize for signed.	Tristan Gingold	2019-09-11	1	-0/+15
\|
*	synth: improve support of return statement.	Tristan Gingold	2019-09-11	8	-21/+117
\|
*	synth: improve support of negative integer values.	Tristan Gingold	2019-09-11	2	-15/+29
\|
*	synth: add const_x gate.	Tristan Gingold	2019-09-11	4	-1/+27
\|
*	synth: introduce Seq_Context.	Tristan Gingold	2019-09-11	2	-68/+87
\|
*	synth: move synth_user_function_call to synth-stmts.	Tristan Gingold	2019-09-11	3	-60/+62
\|
*	synth: improve support of slices.	Tristan Gingold	2019-09-11	1	-50/+54
\|
*	synth: introduce slice type.	Tristan Gingold	2019-09-11	4	-1/+26
\|
*	synth: Add width field in type_type record.	Tristan Gingold	2019-09-11	6	-109/+119
\|
*	synth: handle alias (WIP, read only).	Tristan Gingold	2019-09-11	7	-12/+86
\|
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	4	-3/+31
\|
*	synth: add const_sb32, add smul/umul.	Tristan Gingold	2019-09-07	6	-13/+105
\|
*	vhdl: recognize numeric_std mul.	Tristan Gingold	2019-09-07	2	-0/+27
\|
*	synth: handle partial assignments in case statements.	Tristan Gingold	2019-09-07	3	-44/+95
\|