| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: completly disable inference with -di. | Tristan Gingold | 2019-09-22 | 1 | -4/+6 |
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| * | synth: handle rotate. | Tristan Gingold | 2019-09-22 | 4 | -45/+71 |
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| * | vhdl: recognize rotate functions. | Tristan Gingold | 2019-09-22 | 4 | -3/+24 |
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| * | synth: handle exit/next statements. | Tristan Gingold | 2019-09-22 | 2 | -5/+207 |
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| * | synth: remove T_En from Seq_Context. | Tristan Gingold | 2019-09-21 | 2 | -34/+20 |
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| * | synth: fix to_unsigned (nat, nat) | Tristan Gingold | 2019-09-21 | 1 | -1/+2 |
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| * | netlists-disp_vhdl: handle lsr. | Tristan Gingold | 2019-09-21 | 1 | -0/+4 |
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| * | synth: use constant for constant values. | Tristan Gingold | 2019-09-21 | 2 | -30/+64 |
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| * | synth: fix tgingold/ghdlsynth-beta#27 | Tristan Gingold | 2019-09-21 | 1 | -1/+2 |
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| * | synth-insts: refactoring | Tristan Gingold | 2019-09-21 | 1 | -27/+12 |
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| * | synth-insts: remove useless function. | Tristan Gingold | 2019-09-21 | 1 | -15/+2 |
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| * | synth: do not create self-instance on black-boxed modules. | Tristan Gingold | 2019-09-21 | 3 | -6/+12 |
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| * | synth: add bit0/bit1 in instance. | Tristan Gingold | 2019-09-21 | 4 | -14/+33 |
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| * | netlists-dump: disp width of outputs in instances. | Tristan Gingold | 2019-09-21 | 1 | -2/+4 |
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| * | synth: add Get_Build (WIP). | Tristan Gingold | 2019-09-20 | 4 | -8/+20 |
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| * | synth: add base_instance. | Tristan Gingold | 2019-09-20 | 4 | -23/+55 |
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| * | synth: rename get/set_module for instances. | Tristan Gingold | 2019-09-20 | 5 | -25/+23 |
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| * | synth-context: get rid off Set_Block_Scope. | Tristan Gingold | 2019-09-20 | 6 | -35/+24 |
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| * | synth-context: make Objects_Array private. | Tristan Gingold | 2019-09-20 | 1 | -1/+2 |
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| * | interning: now based on dyn_interning. | Tristan Gingold | 2019-09-20 | 2 | -106/+25 |
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| * | synth: refactoring to reduce global variables. | Tristan Gingold | 2019-09-19 | 6 | -28/+46 |
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| * | synth: synth_instance_type is now limited. | Tristan Gingold | 2019-09-19 | 1 | -6/+2 |
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| * | synth: make synth_instance_type private. | Tristan Gingold | 2019-09-19 | 7 | -81/+160 |
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| * | synth: handle unconnected out ports. | Tristan Gingold | 2019-09-19 | 1 | -5/+8 |
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| * | synth: handle record subtypes. | Tristan Gingold | 2019-09-19 | 3 | -42/+59 |
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| * | synth: Add support for PSL cover directive (#930) | T. Meissner | 2019-09-19 | 6 | -3/+49 |
| | | | | | | | * synth: Add support for PSL cover directive * testsuite/synth: Add tests for PSL cover directives | ||||
| * | synth: improve locations tracking. | Tristan Gingold | 2019-09-18 | 8 | -7/+84 |
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| * | vhdl: add exit/next flags. | Tristan Gingold | 2019-09-18 | 5 | -63/+173 |
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| * | synth: remove value_mux2. | Tristan Gingold | 2019-09-18 | 5 | -55/+32 |
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| * | synth: fix to get_current_assign_value. | Tristan Gingold | 2019-09-17 | 1 | -7/+4 |
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| * | netlists-dump: add width on extract output. | Tristan Gingold | 2019-09-17 | 1 | -5/+14 |
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| * | synth: add debug flag -dc to not clean. | Tristan Gingold | 2019-09-17 | 3 | -1/+9 |
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| * | synth-inference: detect false loop. | Tristan Gingold | 2019-09-17 | 6 | -2/+335 |
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| * | synth: fold addition on constant nets. | Tristan Gingold | 2019-09-17 | 10 | -49/+178 |
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| * | synth: add synth-flags, add debug option -di. | Tristan Gingold | 2019-09-17 | 3 | -1/+32 |
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| * | synth: minor refactoring about const gates. | Tristan Gingold | 2019-09-15 | 4 | -40/+41 |
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| * | synth-oper: add support of std_match | Tristan Gingold | 2019-09-15 | 1 | -0/+94 |
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| * | synth-disp_vhdl: improve support of boolean, suv. | Tristan Gingold | 2019-09-15 | 1 | -17/+16 |
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| * | synth: add build2_const_vec | Tristan Gingold | 2019-09-15 | 2 | -0/+27 |
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| * | synth-stmts: fix uninitialized variable. | Tristan Gingold | 2019-09-13 | 1 | -1/+9 |
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| * | synth: initialize subprogram variables. | Tristan Gingold | 2019-09-13 | 4 | -8/+14 |
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| * | synth: remove get_width from synth-expr | Tristan Gingold | 2019-09-12 | 3 | -15/+2 |
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| * | synth: extract synth-oper from synth-expr | Tristan Gingold | 2019-09-12 | 6 | -927/+1012 |
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| * | synth: handle simple_aggregate. | Tristan Gingold | 2019-09-12 | 1 | -0/+41 |
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| * | synth: allow empty string literal. | Tristan Gingold | 2019-09-12 | 2 | -2/+4 |
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| * | vhdl-nodes: add a comment. | Tristan Gingold | 2019-09-12 | 1 | -1/+1 |
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| * | synth: handle unsigned shift right | Tristan Gingold | 2019-09-11 | 1 | -0/+7 |
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| * | vhdl-ieee-numeric: recognize shift_right. | Tristan Gingold | 2019-09-11 | 1 | -17/+31 |
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| * | synth: handle unsigned shift left. | Tristan Gingold | 2019-09-11 | 5 | -107/+163 |
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| * | synth: add synth_compare_sgn_sgn | Tristan Gingold | 2019-09-11 | 1 | -0/+23 |
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index : iCE40/ghdl | |
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