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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-028-37/+40
* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-023-9/+62
* synth: remove insert gate.Tristan Gingold2019-08-314-70/+0
* synth: improve synth_uresize.Tristan Gingold2019-08-313-26/+50
* synth: elab subprogram interfaces subtypeTristan Gingold2019-08-311-2/+13
* [PATCH] synth-environment: fix thinkos.Tristan Gingold2019-08-311-14/+57
* synth: add physical division (#904)tgingold2019-08-301-1/+11
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| * synth: added division of physical typeMartin Doerfelt2019-08-301-1/+11
* | synth: add support for --synth on llvm, link with -lm.Tristan Gingold2019-08-302-0/+6
* | synth: fix type elaboration of interfaces.Tristan Gingold2019-08-301-2/+0
* | synth: remove unused const gates.Tristan Gingold2019-08-302-13/+5
* | vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
* | vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
* | synth: ignore report statement.Tristan Gingold2019-08-301-0/+2
* | vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-302-0/+39
* | std_names: add std_matchTristan Gingold2019-08-302-3/+5
* | vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-303-5/+19
* | synth: handle enumeration subtype in ranges.Tristan Gingold2019-08-301-1/+2
* | synth: fix named association in record aggregate.Tristan Gingold2019-08-301-1/+3
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* synth: add support for record types.Tristan Gingold2019-08-2913-82/+361
* synth: Integer operators (#902)marph912019-08-281-0/+16
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-272-0/+3
* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-205-6/+52
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-207-67/+148
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-203-13/+53
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
* vhdl: handle assume in verification units.Tristan Gingold2019-08-205-1/+11
* synth: analyze input files.Tristan Gingold2019-08-201-1/+8
* synth: set location on assume/assert gates.Tristan Gingold2019-08-203-8/+19
* synth: handle verification units.Tristan Gingold2019-08-2013-246/+450
* synth: handle array attribute "length" (#895)marph912019-08-191-0/+10
* synth: fix tgingold/ghdlsynth#34 (association).Tristan Gingold2019-08-171-2/+1
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-1715-363/+549
* synth: handle integer values in subtype conversion.Tristan Gingold2019-08-161-0/+2
* synth: handle integers for displaying vhdl ports.Tristan Gingold2019-08-161-0/+10
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-1612-280/+551
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-166-14/+29
* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-154-4/+149
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
* ghdlsynth: add command to get libghdl paths.Tristan Gingold2019-08-144-22/+97
* ghdldrv: move command_str_disp from ghdlvpi to ghdlmainTristan Gingold2019-08-143-38/+38
* ghdlsynth: declare init_for_ghdl_synth.Tristan Gingold2019-08-141-1/+4