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| author | Sylvain Munaut <tnt@246tNt.com> | 2020-06-02 10:33:21 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-06-03 10:45:31 +0200 |
| commit | ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0 (patch) | |
| tree | 58286dd485e9500c4e12e9a995aaf265555d8c34 /icebox/icebox_vlog.py | |
| parent | cd2610e0fa1c6a90e8e4e4cfe06db1b474e752bb (diff) | |
| download | icestorm-ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0.tar.gz icestorm-ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0.tar.bz2 icestorm-ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0.zip | |
icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k
This allows selection of the div-by-5 mode of the PLL.
This bit can't be fuzzed because it's not supported by the lattice
tools at all ...
This only works for sure on the UP5k.
I tested HX8k and it didn't support it, so I'm only adding this on
the known working FPGA.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'icebox/icebox_vlog.py')
0 files changed, 0 insertions, 0 deletions