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| author | David Shah <davey1576@gmail.com> | 2017-11-29 12:37:40 +0000 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-01-16 15:16:44 +0000 |
| commit | ec3ad586835ec13cd5b3c32f6c2b7580247c562b (patch) | |
| tree | a946b4bc7a87f67f8fcc4372e1296236e3b82d67 /icefuzz | |
| parent | 411bcc53ffc095379f20494cce2da9424e4c5465 (diff) | |
| download | icestorm-ec3ad586835ec13cd5b3c32f6c2b7580247c562b.tar.gz icestorm-ec3ad586835ec13cd5b3c32f6c2b7580247c562b.tar.bz2 icestorm-ec3ad586835ec13cd5b3c32f6c2b7580247c562b.zip | |
Figure out missing SPI config bits, and add to chipdb
Diffstat (limited to 'icefuzz')
| -rw-r--r-- | icefuzz/tests/ip/up5k_I2C_data.txt | 4 | ||||
| -rw-r--r-- | icefuzz/tests/ip/up5k_SPI_data.txt | 8 |
2 files changed, 10 insertions, 2 deletions
diff --git a/icefuzz/tests/ip/up5k_I2C_data.txt b/icefuzz/tests/ip/up5k_I2C_data.txt index a891b0c..f433663 100644 --- a/icefuzz/tests/ip/up5k_I2C_data.txt +++ b/icefuzz/tests/ip/up5k_I2C_data.txt @@ -43,8 +43,8 @@ ("I2C", (25, 31, 0)): { "I2CIRQ": (25, 30, "slf_op_7"), "I2CWKUP": (25, 29, "slf_op_5"), - "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_0"), - "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_1"), + "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_1"), + "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_0"), "SBACKO": (25, 30, "slf_op_6"), "SBADRI0": (25, 30, "lutff_1/in_0"), "SBADRI1": (25, 30, "lutff_2/in_0"), diff --git a/icefuzz/tests/ip/up5k_SPI_data.txt b/icefuzz/tests/ip/up5k_SPI_data.txt index 149c93a..be4be44 100644 --- a/icefuzz/tests/ip/up5k_SPI_data.txt +++ b/icefuzz/tests/ip/up5k_SPI_data.txt @@ -47,6 +47,10 @@ "SOE": (0, 20, "slf_op_5"), "SPIIRQ": (0, 20, "slf_op_2"), "SPIWKUP": (0, 20, "slf_op_3"), + "SPI_ENABLE_0": (7, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (7, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_2": (6, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_3": (6, 0, "cbit2usealt_in_1"), }, ("SPI", (25, 0, 1)): { "MCSNO0": (25, 21, "slf_op_2"), @@ -97,4 +101,8 @@ "SOE": (25, 20, "slf_op_5"), "SPIIRQ": (25, 20, "slf_op_2"), "SPIWKUP": (25, 20, "slf_op_3"), + "SPI_ENABLE_0": (23, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (24, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_2": (23, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_3": (24, 0, "cbit2usealt_in_1"), }, |