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* Update variable name to PYTHON3Miodrag Milanovic2021-09-061-20/+20
* Merge pull request #239 from xobs/python-bin-nameMiodrag Milanović2021-09-061-20/+20
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| * icefuzz: update Makefile to use $(PYTHON) variableSean Cross2019-10-221-20/+20
* | added I2C and SPI for u4k to databaseNils Albartus2020-12-043-0/+539
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* add RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-1010-37/+297
* u4k: add SMCCLK cell locationSimon Schubert2019-02-222-0/+11
* iCE40 Ultra = iCE5LP = u4k portSimon Schubert2019-02-2217-6/+5001
* Added missing ieren entries for lm4k.Andrew Wygle2018-05-131-3/+3
* [WIP] Add partial icebox support for lm4k.Andrew Wygle2018-05-127-1/+213
* Add LM4K to icefuzz Makefile and fuzzconfig.py.Andrew Wygle2018-05-122-0/+24
* Add LM family support to icecube.shAndrew Wygle2018-05-061-0/+56
* Tidy upDavid Shah2018-01-303-1154/+0
* Updated 5k timing data, icetime regression fixDavid Shah2018-01-295-12475/+13771
* DSP related fixesDavid Shah2018-01-281-268/+0
* More DSP timing fuzzing, start adding new tiles to icetimeDavid Shah2018-01-222-0/+3696
* Seperate different DSP configs in timing dataDavid Shah2018-01-2211-2532/+13532
* Fix 5k timing dataDavid Shah2018-01-202-143/+88
* I³C IO reverse engineered and documentedDavid Shah2018-01-162-0/+43
* Remove seperate 5k RAM DB and share with 8k insteadDavid Shah2018-01-165-7167/+4
* Figure out missing SPI config bits, and add to chipdbDavid Shah2018-01-162-2/+10
* Whitespace fixesDavid Shah2017-11-283-9/+36
* Add uncommitted changes and tidy up some filesDavid Shah2017-11-283-2/+253
* Preparations for 5k icetimeDavid Shah2017-11-243-2/+3627
* Documented I2C/SPI/LEDDA_IPDavid Shah2017-11-241-0/+46
* All 5k IP tracedDavid Shah2017-11-244-3/+129
* Work on UltraPlus IP tracingDavid Shah2017-11-243-0/+366
* Begin I2C/SPI IP reverse engineeringDavid Shah2017-11-234-0/+153
* Fix whitespace and a couple of typosDavid Shah2017-11-205-5/+5
* Add missing 5k BRAM bitsDavid Shah2017-11-173-0/+939
* Add support for UltraPlus SPRAMDavid Shah2017-11-172-237/+242
* 5k RGB driver reverse engineeredDavid Shah2017-11-173-0/+195
* Fix 5k corner routing, and reverse engineer SPRAMDavid Shah2017-11-173-0/+406
* Figure out DSP config bits for all locsDavid Shah2017-11-173-0/+142
* Trace DSP routingDavid Shah2017-11-171-1/+3
* Create icefuzz scripts for DSP and 5kDavid Shah2017-11-1713-986/+16479
* Preparations for DSP and IpCon fuzzingDavid Shah2017-11-088-5/+70
* Add more 5k RAM bits to dbDavid Shah2017-11-052-0/+1243
* Add 5k colbuf fuzzing scriptsDavid Shah2017-11-024-0/+172
* PLL configuration fuzzing scriptDavid Shah2017-10-303-0/+316
* Share glb_netwk data between 5k and 8k partsDavid Shah2017-10-291-4/+0
* Add ColBufCtrl bits to database for 5k partsDavid Shah2017-10-251-0/+4
* Add some verilog tests for analysing up5k featuresDavid Shah2017-10-238-0/+216
* Fix IeRen database for up5kDavid Shah2017-10-233-0/+51
* Add DSP and IPConnect tile support to icepack and glbcheckDavid Shah2017-10-211-4/+3
* Fix make_ram40 for UltraPlusDavid Shah2017-10-201-3/+7
* Fix case where make_prim allocates all global buffer pinsDavid Shah2017-10-201-1/+21
* Quick fix of pin 23 issue (pending further discussion)David Shah2017-10-201-1/+3
* Squelch trailing whitespaceLarry Doolittle2017-08-017-9/+6
* Fix some bugs in two of the icefuzz make_*.py scriptsClifford Wolf2017-07-312-2/+2
* Fix icecube.sh to work with lin and lin64 dirs, remove hardcoded ICECUBEDIR=Clifford Wolf2017-07-311-5/+5
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