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| author | gatecat <gatecat@ds0.me> | 2021-06-11 08:38:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-11 08:38:24 +0100 |
| commit | 0a27601c817abbbaf230708ffc0daee5ef6fec61 (patch) | |
| tree | 0ffca21f055ae8b271561344425d1ee75cabd2b5 /fpga_interchange/site_router_tests/lut/test.yaml | |
| parent | 1cc7ee785957c14f83b89d6bf18f14d072e6312e (diff) | |
| parent | 1cd2901d854b969a8cb1afc66e3f3388766776a0 (diff) | |
| download | nextpnr-tests-0a27601c817abbbaf230708ffc0daee5ef6fec61.tar.gz nextpnr-tests-0a27601c817abbbaf230708ffc0daee5ef6fec61.tar.bz2 nextpnr-tests-0a27601c817abbbaf230708ffc0daee5ef6fec61.zip | |
Merge pull request #10 from antmicro/site_router_test_framework
fpga_interchange: Add initial site router test framework
Diffstat (limited to 'fpga_interchange/site_router_tests/lut/test.yaml')
| -rw-r--r-- | fpga_interchange/site_router_tests/lut/test.yaml | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/fpga_interchange/site_router_tests/lut/test.yaml b/fpga_interchange/site_router_tests/lut/test.yaml new file mode 100644 index 0000000..e299d81 --- /dev/null +++ b/fpga_interchange/site_router_tests/lut/test.yaml @@ -0,0 +1,28 @@ +test_case: + - place: + # Place cell `lut_2` at BEL `SLICE_X1Y8.SLICEL/A6LUT` + lut_1: SLICE_X1Y8.SLICEL/A6LUT + - test: + # Make sure this placement is accept + SLICE_X1Y8.SLICEL/A6LUT: true + - unplace: + SLICE_X1Y8.SLICEL/A6LUT + # - place: + # lut_1: SLICE_X1Y8.SLICEL/B6LUT + # - test: + # # Make sure this placement is accept + # SLICE_X1Y8.SLICEL/A6LUT: true + # SLICE_X1Y8.SLICEL/B6LUT: true + # - place: + # lut_1: SLICE_X1Y8.SLICEL/A6LUT + # lut_2: SLICE_X1Y8.SLICEL/A5LUT + # - test: + # # The site is now invalid because too many signals into the A6/A5LUT + # SLICE_X1Y8.SLICEL/A6LUT: false + # SLICE_X1Y8.SLICEL/A5LUT: false + # - unplace: + # - lut_2 + # - test: + # # By removing lut_2, the site is valid again + # SLICE_X1Y8.SLICEL/A6LUT: true + # SLICE_X1Y8.SLICEL/A5LUT: true |