diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-07 13:04:04 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-07 13:04:04 -0800 |
| commit | 31b2cdca145f8fc96424e0c7b6f4000f7c777c12 (patch) | |
| tree | ea76bcfa26734338f499d4842e9440aff36a14f4 /ice40/regressions/issue0071 | |
| parent | 5908b57413f83077f082cf566d0dfbf5e76703b1 (diff) | |
| download | nextpnr-tests-31b2cdca145f8fc96424e0c7b6f4000f7c777c12.tar.gz nextpnr-tests-31b2cdca145f8fc96424e0c7b6f4000f7c777c12.tar.bz2 nextpnr-tests-31b2cdca145f8fc96424e0c7b6f4000f7c777c12.zip | |
Add testcases from GH
Diffstat (limited to 'ice40/regressions/issue0071')
| -rw-r--r-- | ice40/regressions/issue0071/top-nopll.json | 6747 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-nopll.npnr | 1 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-nopll.pcf | 5 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-nopll.v | 35 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-nopll.ys | 3 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-pll.json | 6794 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-pll.npnr | 1 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-pll.pcf | 5 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-pll.v | 51 | ||||
| -rw-r--r-- | ice40/regressions/issue0071/top-pll.ys | 3 |
10 files changed, 13645 insertions, 0 deletions
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diff --git a/ice40/regressions/issue0071/top-nopll.npnr b/ice40/regressions/issue0071/top-nopll.npnr new file mode 100644 index 0000000..7da092a --- /dev/null +++ b/ice40/regressions/issue0071/top-nopll.npnr @@ -0,0 +1 @@ +--lp8k --package cm81 --freq 16.0 diff --git a/ice40/regressions/issue0071/top-nopll.pcf b/ice40/regressions/issue0071/top-nopll.pcf new file mode 100644 index 0000000..f90bf2b --- /dev/null +++ b/ice40/regressions/issue0071/top-nopll.pcf @@ -0,0 +1,5 @@ +set_io clk16 B2
+set_io usb_d_p B4
+set_io usb_d_n A4
+set_io usb_pullup A3
+set_io user_led B3
diff --git a/ice40/regressions/issue0071/top-nopll.v b/ice40/regressions/issue0071/top-nopll.v new file mode 100644 index 0000000..1e8c870 --- /dev/null +++ b/ice40/regressions/issue0071/top-nopll.v @@ -0,0 +1,35 @@ +/* Machine-generated using Migen */
+module top(
+ input clk16,
+ input usb_d_p,
+ input usb_d_n,
+ output usb_pullup,
+ output user_led
+);
+
+wire sys_clk;
+reg sys_rst = 1'd0;
+wire clk16_1;
+reg [23:0] count = 24'd0;
+
+
+// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
+// to run the combinatorial process once at the beginning.
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+
+assign sys_clk = clk16_1;
+assign clk16_1 = clk16;
+assign usb_pullup = 1'd0;
+assign user_led = count[22];
+
+always @(posedge sys_clk) begin
+ count <= (count + 1'd1);
+ if (sys_rst) begin
+ count <= 24'd0;
+ end
+end
+
+endmodule
diff --git a/ice40/regressions/issue0071/top-nopll.ys b/ice40/regressions/issue0071/top-nopll.ys new file mode 100644 index 0000000..4752248 --- /dev/null +++ b/ice40/regressions/issue0071/top-nopll.ys @@ -0,0 +1,3 @@ +read_verilog top.v
+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
+synth_ice40 -top top -json top.json
\ No newline at end of file diff --git a/ice40/regressions/issue0071/top-pll.json b/ice40/regressions/issue0071/top-pll.json new file mode 100644 index 0000000..4067018 --- /dev/null +++ b/ice40/regressions/issue0071/top-pll.json @@ -0,0 +1,6794 @@ +{
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diff --git a/ice40/regressions/issue0071/top-pll.npnr b/ice40/regressions/issue0071/top-pll.npnr new file mode 100644 index 0000000..7da092a --- /dev/null +++ b/ice40/regressions/issue0071/top-pll.npnr @@ -0,0 +1 @@ +--lp8k --package cm81 --freq 16.0 diff --git a/ice40/regressions/issue0071/top-pll.pcf b/ice40/regressions/issue0071/top-pll.pcf new file mode 100644 index 0000000..f90bf2b --- /dev/null +++ b/ice40/regressions/issue0071/top-pll.pcf @@ -0,0 +1,5 @@ +set_io clk16 B2
+set_io usb_d_p B4
+set_io usb_d_n A4
+set_io usb_pullup A3
+set_io user_led B3
diff --git a/ice40/regressions/issue0071/top-pll.v b/ice40/regressions/issue0071/top-pll.v new file mode 100644 index 0000000..49df6c6 --- /dev/null +++ b/ice40/regressions/issue0071/top-pll.v @@ -0,0 +1,51 @@ +/* Machine-generated using Migen */
+module top(
+ input clk16,
+ input usb_d_p,
+ input usb_d_n,
+ output usb_pullup,
+ output user_led
+);
+
+wire sys_clk;
+reg sys_rst = 1'd0;
+wire clk16_1;
+wire clk16b;
+reg [23:0] count = 24'd0;
+
+
+// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
+// to run the combinatorial process once at the beginning.
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+
+assign clk16_1 = clk16;
+assign usb_pullup = 1'd0;
+assign user_led = count[22];
+
+always @(posedge sys_clk) begin
+ count <= (count + 1'd1);
+ if (sys_rst) begin
+ count <= 24'd0;
+ end
+end
+
+SB_PLL40_CORE #(
+ .DIVF(6'd63),
+ .DIVQ(3'd6),
+ .DIVR(1'd0),
+ .FILTER_RANGE(3'd1)
+) SB_PLL40_CORE (
+ .REFERENCECLK(clk16_1),
+ .RESETB(1'd1),
+ .PLLOUTCORE(clk16b)
+);
+
+SB_GB SB_GB(
+ .USER_SIGNAL_TO_GLOBAL_BUFFER(clk16b),
+ .GLOBAL_BUFFER_OUTPUT(sys_clk)
+);
+
+endmodule
diff --git a/ice40/regressions/issue0071/top-pll.ys b/ice40/regressions/issue0071/top-pll.ys new file mode 100644 index 0000000..4752248 --- /dev/null +++ b/ice40/regressions/issue0071/top-pll.ys @@ -0,0 +1,3 @@ +read_verilog top.v
+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
+synth_ice40 -top top -json top.json
\ No newline at end of file |