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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-09 10:56:42 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-09 10:56:42 -0800 |
commit | c16195dbb7baa281accb3e41ad479a02f5e47d6c (patch) | |
tree | 5869d5be87da8662c8aaa05ff6858360b0408800 /ice40/regressions/issue0148/hdl/simram.sv | |
parent | f28a055c3531bf7e8b3c744b00e6b1ff1e89b292 (diff) | |
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YosysHQ/nextpnr#148
Diffstat (limited to 'ice40/regressions/issue0148/hdl/simram.sv')
-rw-r--r-- | ice40/regressions/issue0148/hdl/simram.sv | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/ice40/regressions/issue0148/hdl/simram.sv b/ice40/regressions/issue0148/hdl/simram.sv new file mode 100644 index 0000000..fc87f07 --- /dev/null +++ b/ice40/regressions/issue0148/hdl/simram.sv @@ -0,0 +1,40 @@ +// Copyright 2015, Brian Swetland <swetland@frotz.net> +// Licensed under the Apache License, Version 2.0. + +`timescale 1ns / 1ps + +import "DPI-C" function void dpi_mem_write(int addr, int data); +import "DPI-C" function void dpi_mem_read(int addr, output int data); + +module simram( + input clk, + input [15:0]waddr, + input [15:0]wdata, + input we, + input [15:0]raddr, + output reg [15:0]rdata, + input re + ); + + wire [31:0]rawdata; + wire [31:0]junk; + + // hack: this should be posedge but if we do that + // then the dpi_mem_write() happens too early + always @(negedge clk) begin + if (we) begin + $display(":WRI %08x %08x", waddr, wdata); + dpi_mem_write({16'd0, waddr}, {16'd0, wdata}); + end + end + always @(posedge clk) begin + if (re) begin + dpi_mem_read({16'd0, raddr}, rawdata); + rdata <= rawdata[15:0]; + end else begin + //junk = $random(); + //rdata <= junk[15:0]; + rdata <= 16'hEEEE; + end + end +endmodule |