YosysHQ/nextpnr#148

27 files changed, 57261 insertions, 0 deletions

diff --git a/ice40/regressions/issue0148/ATTRIBUTION b/ice40/regressions/issue0148/ATTRIBUTION
new file mode 100644
index 0000000..0242850
--- /dev/null
+++ b/ice40/regressions/issue0148/ATTRIBUTION
@@ -0,0 +1 @@
+https://github.com/swetland/cpu16/tree/ffc013add5208852276d815ab3af5dca26684764
diff --git a/ice40/regressions/issue0148/hdl/cpu/alu.v b/ice40/regressions/issue0148/hdl/cpu/alu.v
new file mode 100644
index 0000000..d6f5100
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/cpu/alu.v
@@ -0,0 +1,53 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+module alu #(
+	parameter DWIDTH = 16,
+	parameter SWIDTH = 4
+	)(
+	input [3:0]op,
+	input [DWIDTH-1:0]adata,
+	input [DWIDTH-1:0]bdata,
+	output reg[DWIDTH-1:0]rdata
+	);
+
+`ifdef BIT_OPS
+wire [DWIDTH-1:0]bits = (1 << bdata[SWIDTH-1:0]);
+`endif
+
+always @(*) begin
+	case (op)
+	4'b0000: rdata = bdata;
+	4'b0001: rdata = adata & bdata;
+	4'b0010: rdata = adata | bdata;
+	4'b0011: rdata = adata ^ bdata;
+	4'b0100: rdata = adata + bdata;
+	4'b0101: rdata = adata - bdata;
+	4'b0110: rdata = adata * bdata;
+	4'b0111: rdata = { bdata[7:0], adata[7:0] };
+	4'b1000: rdata = { {(DWIDTH-1){1'b0}}, adata < bdata };
+	4'b1001: rdata = { {(DWIDTH-1){1'b0}}, adata <= bdata };
+`ifdef FULL_SHIFTER
+	4'b1010: rdata = adata >> bdata[SWIDTH-1:0];
+	4'b1011: rdata = adata << bdata[SWIDTH-1:0];
+`else
+	4'b1010: rdata = { 1'b0, adata[DWIDTH-1:1] };
+	4'b1011: rdata = { adata[DWIDTH-2:0], 1'b0 };
+`endif
+`ifdef BIT_OPS
+	4'b1100: rdata = adata | bits;
+	4'b1101: rdata = adata & (~bits);
+	4'b1110: rdata = adata & bits;
+	4'b1111: rdata = bits;
+`else
+	4'b1100: rdata = {DWIDTH{1'bX}};
+	4'b1101: rdata = {DWIDTH{1'bX}};
+	4'b1110: rdata = {DWIDTH{1'bX}};
+	4'b1111: rdata = {DWIDTH{1'bX}};
+`endif
+	endcase
+end
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/cpu/cpu.v b/ice40/regressions/issue0148/hdl/cpu/cpu.v
new file mode 100644
index 0000000..e1352e1
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/cpu/cpu.v
@@ -0,0 +1,388 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+module cpu #(
+	parameter RWIDTH = 16,
+	parameter SWIDTH = 4
+	)(
+	input clk,
+`ifdef WITH_DEBUG
+	output [RWIDTH-1:0]debug_data
+	output [3:0]debug_op,
+	output debug_wr,
+`endif
+	output [15:0]mem_raddr_o,
+	input [15:0]mem_rdata_i,
+	output [15:0]mem_waddr_o,
+	output [15:0]mem_wdata_o,
+	output mem_wr_o,
+	output mem_rd_o,
+	input reset
+	);
+
+localparam AWIDTH = 16;
+localparam DWIDTH = 16;
+localparam IWIDTH = 16;
+
+// control signals
+reg do_fetch;
+reg do_load;
+reg do_store;
+wire do_wreg;
+reg [1:0]do_sel_bdata;
+reg [1:0]do_sel_wsel;
+reg [1:0]do_sel_branch;
+reg [1:0]do_sel_alu_op;
+reg do_exe_alu;
+reg do_exe_load;
+reg do_exe_branch;
+reg do_load_pc;
+
+// processor registers
+reg [AWIDTH-1:0]pc = 16'b0;
+reg [15:0]ir = 16'b0;
+reg ir_valid = 1'b0;
+reg ir_loading = 1'b0;
+
+reg [AWIDTH-1:0]pc_next;
+reg [15:0]ir_next;
+reg ir_valid_next;
+reg ir_loading_next;
+
+// registers that allow/disallow EXEC/LOAD and IMMEDIATE
+reg exe_alu = 1'b0;
+reg exe_load = 1'b0;
+reg exe_branch = 1'b0;
+
+// registers loaded during DECODE for use in EXEC/LOAD
+reg [3:0]alu_op = 4'b0;
+reg [RWIDTH-1:0]adata = 16'b0;
+reg [RWIDTH-1:0]bdata = 16'b0;
+reg [3:0]wsel = 4'b0;
+
+// in/out of alu
+wire [RWIDTH-1:0]alu_rdata;
+
+// values computed 
+wire [3:0]ir_asel = ir[7:4];
+wire [3:0]ir_bsel = ir[11:8];
+wire [RWIDTH-1:0]ir_imm_s4 =  { {(RWIDTH-3) {ir[15]}}, ir[14:12] };
+wire [RWIDTH-1:0]ir_imm_s8 =  { {(RWIDTH-7) {ir[15]}}, ir[14:8] };
+wire [RWIDTH-1:0]ir_imm_s12 = { {(RWIDTH-11){ir[15]}}, ir[14:4] };
+
+// in/out of reg file
+wire [3:0]regs_asel = ir_asel;
+wire [3:0]regs_bsel = ir_bsel;
+wire [RWIDTH-1:0]regs_wdata = exe_load ? { {(RWIDTH-DWIDTH){1'b0}}, mem_rdata_i } : alu_rdata;
+wire [RWIDTH-1:0]regs_adata;
+wire [RWIDTH-1:0]regs_bdata;
+
+wire [RWIDTH-1:0]load_store_addr = regs_bdata + ir_imm_s4;
+
+wire [AWIDTH-1:0]new_pc = exe_branch ? branch_target : (pc + 16'd1);
+
+reg [AWIDTH-1:0]branch_target;
+
+localparam BR_REL_S8  = 2'b00; // PC + S8   a short branch
+localparam BR_REL_S12 = 2'b01; // PC + S12  a long branch
+localparam BR_ABS_RB  = 2'b10; // RB        an indirect branch
+
+wire [RWIDTH-1:0]branch_imm = do_sel_branch[0] ? ir_imm_s12 : ir_imm_s8;
+wire [RWIDTH-1:0]branch_tgt = do_sel_branch[1] ? regs_bdata : (pc + branch_imm);
+wire [AWIDTH-1:0]branch_target_next = branch_tgt[AWIDTH-1:0];
+
+// memory interface
+assign mem_wr_o = do_store;
+assign mem_rd_o = 1;
+assign mem_raddr_o = do_load ? load_store_addr[AWIDTH-1:0] : pc_next;
+assign mem_waddr_o = load_store_addr[AWIDTH-1:0];
+assign mem_wdata_o = regs_adata[AWIDTH-1:0];
+
+always_comb begin
+	ir_next = ir;
+	ir_valid_next = ir_valid;
+	ir_loading_next = ir_loading;
+
+	do_load_pc = 1'b0;
+
+	// we try to read an instruction every cycle
+	// unless we're pre-empted by a data load
+	//XXX don't issue a read if we know it's useless?
+	ir_loading_next = ~do_load;
+
+	if (exe_branch) begin
+		// branch is always highest priority
+		ir_valid_next = 1'b0;
+		do_load_pc = 1'b1;
+	end else if (ir_loading) begin
+		// we've read an instruction
+		if ((~ir_valid) | do_fetch) begin
+			// ir was empty or is being consumed
+			// fill it with the just-read instruction
+			// and advance the pc
+			ir_next = mem_rdata_i;
+			ir_valid_next = 1'b1;
+			do_load_pc = 1'b1;
+		end else if (do_fetch) begin
+			// ir has been consumed if it was non-empty
+			ir_valid_next = 1'b0;
+		end
+	end else begin
+		// not loading
+		if (do_fetch) begin
+			ir_valid_next = 1'b0;
+		end
+	end
+
+	pc_next = do_load_pc ? new_pc : pc;
+end
+
+/*
+always_ff @(posedge clk) begin
+	pc <= reset ? 16'd0 : pc_next;
+	ir_valid <= reset ? 1'd0 : ir_valid_next;
+	ir_loading <= reset ? 1'd0 : ir_loading_next;
+	ir <= ir_next;
+end
+*/
+
+always_ff @(posedge clk) begin
+	if (reset) begin
+		pc <= 16'd0;
+		ir_valid <= 1'd0;
+		ir_loading <= 1'd0;
+	end else begin
+		pc <= pc_next;
+		ir_valid <= ir_valid_next;
+		ir_loading <= ir_loading_next;
+	end
+	ir <= ir_next;
+end
+
+localparam BDATA_RB = 2'b00;
+localparam BDATA_PC = 2'b01;
+localparam BDATA_S4 = 2'b10; 
+localparam BDATA_S8 = 2'b11;
+reg [RWIDTH-1:0]bdata_mux;
+always_comb begin
+	case (do_sel_bdata)
+	BDATA_RB: bdata_mux = regs_bdata;
+	BDATA_PC: bdata_mux = pc;
+	BDATA_S4: bdata_mux = ir_imm_s4;
+	BDATA_S8: bdata_mux = ir_imm_s8;
+	endcase
+end
+
+localparam WSEL_RA = 2'b00;
+localparam WSEL_RB = 2'b01;
+localparam WSEL_OP = 2'b10;
+localparam WSEL_LR = 2'b11;
+reg [3:0]wsel_mux;
+always_comb begin
+	case (do_sel_wsel)
+	WSEL_RA: wsel_mux = ir[7:4];
+	WSEL_RB: wsel_mux = ir[11:8];
+	WSEL_OP: wsel_mux = { 2'b0, ir[1:0] };
+	WSEL_LR: wsel_mux = 4'd14;
+	endcase
+end
+
+localparam ALU_MOV = 2'b00;
+localparam ALU_MHI = 2'b01;
+localparam ALU_FN_HI = 2'b10;
+localparam ALU_FN_LO = 2'b11;
+reg [3:0]alu_op_mux;
+always_comb begin
+	case (do_sel_alu_op)
+	ALU_MOV:   alu_op_mux = 4'b0000;
+	ALU_MHI:   alu_op_mux = 4'b0111;
+	ALU_FN_HI: alu_op_mux = ir[15:12];
+	ALU_FN_LO: alu_op_mux = ir[11:8];
+	endcase
+end
+
+wire regs_adata_zero = (regs_adata == 16'd0);
+
+assign do_wreg = exe_alu | exe_load;
+
+//`define WITH_BYPASS
+
+localparam USE_RA =    2'b10;
+localparam USE_RB =    2'b01;
+localparam USE_RA_RB = 2'b11;
+localparam USE_NONE =  2'b00;
+reg [1:0]using;
+wire conflict_a = (wsel == ir_asel) & using[1];
+wire conflict_b = (wsel == ir_bsel) & using[0];
+
+`ifdef WITH_DEBUG
+assign debug_op = ir_bsel;
+assign debug_data = regs_adata;
+assign debug_wr = do_fetch & ir_valid & (ir[15:12] == 4'b0010) & (ir[3:0] == 4'b1110);
+`endif
+
+always_comb begin
+	// decode stage
+	do_fetch =       1'b1;
+	do_load =        1'b0;
+	do_store =       1'b0;
+	do_sel_branch =  BR_ABS_RB;
+	do_sel_bdata =   BDATA_RB;
+	do_sel_wsel =    WSEL_RA;
+	do_sel_alu_op =  ALU_MOV;
+
+	do_exe_alu =     1'b0;
+	do_exe_load =    1'b0;
+	do_exe_branch =  1'b0;
+
+	using = USE_RA_RB;
+
+	if (exe_branch) begin
+		do_fetch = 1'b0;
+	end
+`ifndef WITH_BYPASS
+	else if (exe_alu | exe_load) begin
+		do_fetch = ~(conflict_a | conflict_b);
+	end
+`endif
+
+	casez (ir[3:0])
+	4'b0000: begin // mov Ra, imm
+		using = USE_NONE;
+		do_exe_alu = 1'b1;
+		do_sel_alu_op = ALU_MOV;
+		do_sel_wsel = WSEL_RA;
+		do_sel_bdata = BDATA_S8;
+	end
+	4'b0001: begin // mhi Ra, imm
+		using = USE_RA;
+		do_exe_alu = 1'b1;
+		do_sel_alu_op = ALU_MHI;
+		do_sel_wsel = WSEL_RA;
+		do_sel_bdata = BDATA_S8;
+	end
+	4'b0010: begin // alu Ra, Ra, Rb
+		using = USE_RA_RB;
+		do_exe_alu = 1'b1;
+		do_sel_alu_op = ALU_FN_HI;
+		do_sel_wsel = WSEL_RA;
+		do_sel_bdata = BDATA_RB;
+	end
+	4'b0011: begin // alu Ra, Ra, imm4
+		using = USE_RA;
+		do_exe_alu = 1'b1;
+		do_sel_alu_op = ALU_FN_LO;
+		do_sel_wsel = WSEL_RA;
+		do_sel_bdata = BDATA_S4;
+	end
+	4'b01??: begin // alu Rd, Ra, Rb
+		using = USE_RA_RB;
+		do_exe_alu = 1'b1;
+		do_sel_alu_op = ALU_FN_HI;
+		do_sel_wsel = WSEL_OP;
+		do_sel_bdata = BDATA_RB;
+	end
+	4'b1000: begin // lw Ra, [Rb, imm]
+		using = USE_RB;
+		do_exe_load = 1'b1;
+		do_load = ir_valid;
+	end
+	4'b1001: begin // sw Ra, [Rb, imm]
+		using = USE_RA_RB;
+		do_store = ir_valid;
+	end
+	4'b1010: begin // bnz Ra, rel8
+		using = USE_RA;
+		do_exe_branch = ~regs_adata_zero;
+		do_sel_branch = BR_REL_S8;
+	end
+	4'b1011: begin // bz Ra, rel8
+		using = USE_RA;
+		do_exe_branch = regs_adata_zero;
+		do_sel_branch = BR_REL_S8;
+	end
+	4'b1100: begin // b rel12
+		using = USE_NONE;
+		do_exe_branch = 1'b1;
+		do_sel_branch = BR_REL_S12;
+	end
+	4'b1101: begin // bl rel12
+		using = USE_NONE;
+		do_exe_alu = 1'b1;
+		do_exe_branch = 1'b1;
+		do_sel_branch = BR_REL_S12;
+		do_sel_alu_op = ALU_MOV;
+		do_sel_bdata = BDATA_PC;
+		do_sel_wsel = WSEL_LR;
+	end
+	4'b1110: begin
+		if (ir[15:13] == 3'b000) begin // b Rb / bl Rb
+			using = USE_RB;
+			do_exe_branch = 1'b1;
+			do_sel_branch = BR_ABS_RB;
+			if (ir[12]) begin
+				do_exe_alu = 1'b1;
+				do_sel_alu_op = ALU_MOV;
+				do_sel_bdata = BDATA_PC;
+				do_sel_wsel = WSEL_LR;
+			end
+		end
+	end
+	default: begin
+		// treat undefined as NOP
+	end
+	endcase
+end
+
+always_ff @(posedge clk) begin
+	alu_op <= alu_op_mux;
+	adata <= regs_adata;
+	bdata <= bdata_mux;
+	wsel <= wsel_mux;
+	exe_alu <= ir_valid & do_fetch & do_exe_alu;
+	exe_load <= ir_valid & do_fetch & do_exe_load;
+	exe_branch <= ir_valid & do_fetch & do_exe_branch;
+	branch_target <= branch_target_next;
+
+end
+
+wire [RWIDTH-1:0]raw_regs_adata;
+wire [RWIDTH-1:0]raw_regs_bdata;
+
+regfile #(
+	.DWIDTH(RWIDTH)
+	)regs(
+	.clk(clk),
+	.asel(regs_asel),
+	.bsel(regs_bsel),
+	.adata(raw_regs_adata),
+	.bdata(raw_regs_bdata),
+	.wsel(wsel),
+	.wdata(regs_wdata),
+	.wreg(do_wreg)
+	);
+
+`ifdef WITH_BYPASS
+wire bypass_a = do_wreg & (wsel == ir_asel) & (~exe_load);
+wire bypass_b = do_wreg & (wsel == ir_bsel) & (~exe_load);
+assign regs_adata = bypass_a ? regs_wdata : raw_regs_adata;
+assign regs_bdata = bypass_b ? regs_wdata : raw_regs_bdata;
+`else
+assign regs_adata = raw_regs_adata;
+assign regs_bdata = raw_regs_bdata;
+`endif
+
+alu #(
+	.DWIDTH(RWIDTH),
+	.SWIDTH(SWIDTH)
+	)alu0(
+	.op(alu_op),
+	.adata(adata),
+	.bdata(bdata),
+	.rdata(alu_rdata)
+	);
+
+endmodule
+
diff --git a/ice40/regressions/issue0148/hdl/cpu/isa.txt b/ice40/regressions/issue0148/hdl/cpu/isa.txt
new file mode 100644
index 0000000..225a53b
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/cpu/isa.txt
@@ -0,0 +1,66 @@
+
+Basic Instructions     Assembly Syntax       Operation
+---------------------  --------------------  -----------------------------
+iiii iiii aaaa 0000    mov Ra, si8           Ra = si8
+iiii iiii aaaa 0001    mhi Ra, si8           Ra = (Ra & 0xFF) | (si8 << 8)
+ffff bbbb aaaa 0010    alu Ra, Ra, Rb        Ra = Ra <fn> Rb
+iiii ffff aaaa 0011    alu Ra, Ra, si4       Ra = Ra <fn> si4
+ffff bbbb aaaa 01cc    alu Rc, Ra, Rb        Rc = Ra <fn> Rb
+iiii bbbb aaaa 1000    lw Ra, [Rb, si4]      Ra = [Rb + si4]
+iiii bbbb aaaa 1001    sw Ra, [Rb, si4]      [Rb + si4] = Ra
+iiii iiii aaaa 1010    bnz Ra, si8           if (Ra != 0) PC += si8
+iiii iiii aaaa 1011    bz Ra, si8            if (Ra == 0) PC += si8
+iiii iiii iiii 1100    b si12                PC += si12
+iiii iiii iiii 1101    bl si12               R14 = PC, PC += si12,
+0000 bbbb xxxx 1110    b Rb                  PC = Rb
+0001 bbbb xxxx 1110    bl Rb                 R14 = PC, PC = Rb
+0010 0000 0000 1110    nop
+0010 nnnn aaaa 1110    debug Ra, x4          DEBUG(Ra, n4)
+
+Extended Instructions                  <--- Not implemented yet.
+---------------------                       Will likely change during
+0011 xxxx xxxx 1110    iret                 implementation.
+0100 nnnn aaaa 1110    mov Ra, Sn
+0101 nnnn aaaa 1110    mov Sn, Ra
+0110 aaaa bbbb 1110    mov Ra', Rb
+0111 aaaa bbbb 1110    mov Ra, Rb'
+1xxx xxxx xxxx 1110    undefined
+nnnn nnnn 0000 1111    syscall n
+nnnn nnnn 0001 1111    break;
+nnnn nnnn 0010 1111    set <flags>
+nnnn nnnn 0011 1111    clr <flags>
+xxxx xxxx 0011 1111    undefined
+xxxx xxxx 01xx 1111    undefined
+xxxx xxxx 1xxx 1111    undefined
+
+ALU Functions (<fn>)                     Key
+--------------------------------------   ----------------------------------
+0000 mov   r = b                         si4      signed 4bit immediate
+0001 and   r = a & b                     si8      signed 8bit immediate
+0010 orr   r = a | b                     si12     signed 12bit immediate
+0011 xor   r = a ^ b                     fn       ALU function
+0100 add   r = a + b                     R0-R15   general purpose registers
+0101 sub   r = a - b                     PC       program counter
+0110 mul   r = a * b                     
+0111 mhi   r = (b << 8) | (a & 0xFF)     S0-S15   system control registers
+1000 slt   r = a < b                     F0-F7    system flag bits
+1001 sle   r = a <= b                    R0'-R15' banked registers
+1010 shr   r = a >> 1
+1011 shl   r = a << 1
+1100 bis   r = a | (1 << b[3:0])
+1101 bic   r = a & (~(1 << b[3:0]))
+1110 tbs   r = a & (1 << b[3:0])
+1111 bit   r = 1 << b[3:0]
+
+Register Usage / Procedure Call Standard
+-----------------------------------------
+R0 - R3    parameters & results
+R4 - R11   caller save, working variables
+R12        reserved for OS/runtime global use
+R13        stack pointer
+R14        link register* (for branch-and-link)
+R15        scratch (for assembler/linker use)
+
+* The processor can *only* save PC to R14 on BL calls.
+  All other register assignements are merely to simplify
+  software interworking, not required by the architecture.
diff --git a/ice40/regressions/issue0148/hdl/cpu/regfile.v b/ice40/regressions/issue0148/hdl/cpu/regfile.v
new file mode 100644
index 0000000..c5345f3
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/cpu/regfile.v
@@ -0,0 +1,29 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+module regfile #(
+	parameter AWIDTH = 4,
+	parameter DWIDTH = 16
+	)(
+	input clk,
+	input [AWIDTH-1:0]asel,
+	input [AWIDTH-1:0]bsel,
+	input [AWIDTH-1:0]wsel,
+	input wreg,
+	output [DWIDTH-1:0]adata,
+	output [DWIDTH-1:0]bdata,
+	input [DWIDTH-1:0]wdata
+	);
+
+reg [DWIDTH-1:0] R[0:((1<<AWIDTH)-1)];
+
+always @(posedge clk) begin
+	if (wreg)
+		R[wsel] <= wdata;
+end
+assign adata = R[asel];
+assign bdata = R[bsel];
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/cpu16.sv b/ice40/regressions/issue0148/hdl/cpu16.sv
new file mode 100644
index 0000000..91d32b6
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/cpu16.sv
@@ -0,0 +1,303 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+module cpu16(
+        input clk,
+        output [15:0]ins_rd_addr,
+        input [15:0]ins_rd_data,
+	output ins_rd_req,
+	input ins_rd_rdy,
+
+	output [15:0]dat_rw_addr,
+	output [15:0]dat_wr_data,
+	input [15:0]dat_rd_data,
+	output dat_rd_req,
+	output dat_wr_req,
+	input dat_rd_rdy,
+	input dat_wr_rdy,
+
+	input reset
+        );
+
+localparam INS_NOP = 16'h0001;
+
+// ---- FETCH ----
+reg [15:0]pc_next;
+reg [15:0]ir_next;
+reg ir_valid_next;
+
+reg [15:0]pc = 16'd0;
+reg [15:0]ir = 16'd0;
+reg ir_valid = 1'b0;
+
+assign ins_rd_addr = pc_next;
+assign ins_rd_req = 1'b1;
+
+always_comb begin
+	if (reset) begin
+		pc_next = 16'h0000;
+	end else if (ex_do_branch_imm) begin
+		pc_next = ex_branch_tgt;
+	end else if (ins_rd_rdy) begin
+		pc_next = pc + 16'h0001;
+	end else begin
+		pc_next = pc;
+	end
+	ir_next = ins_rd_rdy ? ins_rd_data : INS_NOP;
+	ir_valid_next = ins_rd_rdy;
+end
+
+always_ff @(posedge clk) begin
+	pc <= pc_next;
+	ir <= ir_next;
+	ir_valid <= ir_valid_next;
+end
+
+// ---- DECODE ----
+reg [11:0]de_ext = 12'b0;
+reg de_ext_rdy = 1'b0;
+
+// s6   alu-reg-imm  load/store
+// s7   pc-rel-cond-branch
+// s9   mov-imm
+// s11  pc-rel-branch
+// s12  ext
+
+// fields decoded from instruction
+wire [15:0]ir_imm_s6_raw = { {11 {ir[15]}}, ir[14:10] };
+wire [15:0]ir_imm_s7 = { {10 {ir[15]}}, ir[6], ir[14:10] };
+wire [15:0]ir_imm_s9_raw = { {8 {ir[15]}}, ir[9:7], ir[14:10] };
+wire [15:0]ir_imm_s11 = { {6 {ir[15]}}, ir[8:4], ir[14:10] };
+wire [15:0]ir_imm_s12 = { {5 {ir[15]}}, ir[9:4], ir[14:10] };
+wire [2:0]ir_csel = ir[6:4];
+wire [2:0]ir_asel = ir[9:7];
+wire [2:0]ir_bsel = ir[12:10];
+wire [2:0]ir_alu_op = ir[3] ? ir[2:0] : ir[15:13];
+wire [3:0]ir_opcode = ir[3:0];
+
+reg [11:0]ir_ext_imm = 12'b0;
+reg ir_ext_rdy = 1'b0;
+
+wire [15:0]ir_imm_s6 = { (ir_ext_rdy ? ir_ext_imm : ir_imm_s6_raw[15:4]), ir_imm_s6_raw[3:0] };
+wire [15:0]ir_imm_s9 = { (ir_ext_rdy ? ir_ext_imm : ir_imm_s9_raw[15:4]), ir_imm_s9_raw[3:0] };
+
+// control signals
+reg do_wreg_alu; // write from alu
+reg do_wreg_mem; // write from memory
+reg do_adata_zero; // pass 0 to alu.xdata (instead of adata)
+reg do_bdata_imm; // pass imm to alu.ydata (instead of bdata)
+reg do_wr_link;    // write PC + 1 to LR
+reg do_branch_imm; // branch to imm
+reg do_branch_reg; // branch to reg + imm
+reg do_branch_cond; // branch if condition met
+reg do_branch_zero; // condition zero(1) or notzero(0)
+reg do_use_imm9_or_imm6;
+reg do_mem_read;
+reg do_mem_write;
+reg do_set_ext;
+
+always_comb begin
+	do_wreg_alu = 1'b0;
+	do_wreg_mem = 1'b0;
+	do_adata_zero = 1'b0;
+	do_bdata_imm = 1'b0;
+	do_wr_link = 1'b0;
+	do_branch_imm = 1'b0;
+	do_branch_reg = 1'b0;
+	do_branch_cond = 1'b0;
+	do_branch_zero = 1'b0;
+	do_use_imm9_or_imm6 = 1'b0;
+	do_mem_read = 1'b0;
+	do_mem_write = 1'b0;
+	do_set_ext = 1'b0;
+
+	casez (ir_opcode)
+	4'b0000: begin // alu Rc, Ra, Rb
+		do_wreg_alu = 1'b1;
+	end
+	4'b0001: begin // expansion (nop)
+	end
+	4'b0010: begin // ext si12
+		do_set_ext = 1'b1;
+	end
+	4'b0011: begin // mov Rc, si9
+		do_wreg_alu = 1'b1;
+		do_adata_zero = 1'b1;
+		do_bdata_imm = 1'b1;
+		do_use_imm9_or_imm6 = 1'b1;
+	end
+	4'b0100: begin // lw Rc, [Ra, si6]
+		do_mem_read = 1'b1;
+		do_use_imm9_or_imm6 = 1'b0;
+	end
+	4'b0101: begin // sw Rc, [Ra, si6]
+		do_mem_write = 1'b1;
+		do_use_imm9_or_imm6 = 1'b0;
+	end
+	4'b0110: begin // b imm12 / bl imm12
+		do_branch_imm = 1'b1;
+		do_wr_link = ir[9];
+	end
+	4'b0111: begin // BZ/BNZ/B/BL
+		if (ir[5]) begin // b Ra / bl Ra
+			do_branch_reg = 1'b1;
+			do_wr_link = ir[4];
+		end else begin // bz imm7 / bnz imm7
+			do_branch_cond = 1'b1;
+			do_branch_zero = ~ir[4];
+		end
+	end
+	4'b1???: begin // alu Rc, Ra, si6
+		do_wreg_alu = 1'b1;
+		do_bdata_imm = 1'b1;
+		do_use_imm9_or_imm6 = 1'b0;
+	end
+	endcase
+end
+
+always_ff @(posedge clk) begin
+	if (ir_valid)
+		ir_ext_rdy <= do_set_ext;
+	if (ir_valid & do_set_ext)
+		ir_ext_imm <= ir_imm_s12[11:0];
+end
+
+wire [15:0]ex_adata;
+wire [15:0]ex_bdata;
+wire [15:0]ex_alu_rdata;
+
+regs16 regs(
+	.clk(clk),
+	.asel(ir_asel),
+	.bsel(do_mem_write ? ir_csel : ir_bsel),
+	.wsel(ex_wsel),
+	.wreg(ex_do_wreg_alu),
+	.adata(ex_adata),
+	.bdata(ex_bdata),
+	.wdata(ex_alu_rdata)
+	);
+
+// ---- EXECUTE ----
+
+reg [15:0]ex_branch_tgt = 16'b0;
+reg [2:0]ex_alu_op = 3'b0;
+reg [2:0]ex_wsel = 3'b0;
+reg ex_do_wreg_alu = 1'b0;
+reg ex_do_wreg_mem = 1'b0;
+reg ex_do_adata_zero = 1'b0;
+reg ex_do_bdata_imm = 1'b0;
+reg ex_do_wr_link = 1'b0;
+reg ex_do_branch_imm = 1'b0;
+reg ex_do_branch_reg = 1'b0;
+reg ex_do_branch_cond = 1'b0;
+reg ex_do_branch_zero = 1'b0;
+reg ex_do_mem_read = 1'b0;
+reg ex_do_mem_write = 1'b0;
+
+reg [15:0]ex_imm = 16'b0;
+
+always_ff @(posedge clk) begin
+	// for mem-read or mem-write we use the ALU for Ra + imm7
+	ex_alu_op <= (do_adata_zero | do_mem_read | do_mem_write) ? 3'b0 : ir_alu_op;
+	ex_wsel <= do_wr_link ? 3'd7 : ir_csel;
+	ex_branch_tgt <= pc + (do_branch_imm ? ir_imm_s11 : ir_imm_s7);
+	ex_do_wreg_alu <= do_wreg_alu;
+	ex_do_wreg_mem <= do_wreg_mem;
+	ex_do_adata_zero <= do_adata_zero;
+	ex_do_bdata_imm <= do_bdata_imm;
+	ex_do_wr_link <= do_wr_link;
+	ex_do_branch_imm <= do_branch_imm;
+	ex_do_branch_reg <= do_branch_reg;
+	ex_do_branch_cond <= do_branch_cond;
+	ex_do_branch_zero <= do_branch_zero;
+	ex_do_mem_read = do_mem_read;
+	ex_do_mem_write = do_mem_write;
+	ex_imm <= (do_mem_read | do_mem_write) ? ir_imm_s7 : (do_use_imm9_or_imm6 ? ir_imm_s9 : ir_imm_s6);
+end
+
+
+alu16 alu(
+	.op(ex_alu_op),
+	.xdata(ex_do_adata_zero ? 16'b0 : ex_adata),
+	.ydata((ex_do_mem_read | ex_do_mem_write | ex_do_bdata_imm) ? ex_imm : ex_bdata),
+	.rdata(ex_alu_rdata)
+	);
+
+assign dat_rw_addr = ex_alu_rdata;
+assign dat_wr_data = ex_bdata;
+assign dat_rd_req = ex_do_mem_read;
+assign dat_wr_req = ex_do_mem_write;
+
+// ---- SIMULATION DEBUG ASSIST ----
+
+`ifdef verilator
+reg [15:0]dbg_addr = 16'd0;
+wire [47:0]ir_dbg_dis;
+reg [47:0]ex_dbg_dis = 48'd0;
+
+assign ir_dbg_dis = { ir, 3'b0, ir_ext_rdy, ir_ext_imm, dbg_addr };
+
+always_ff @(posedge clk) begin
+	dbg_addr <= pc;
+	ex_dbg_dis <= ir_dbg_dis;
+end
+`endif
+
+endmodule
+
+module regs16(
+	input clk,
+	input [2:0]asel,
+	input [2:0]bsel,
+	input [2:0]wsel,
+	input wreg,
+	input [15:0]wdata,
+	output [15:0]adata,
+	output [15:0]bdata
+	);
+
+reg [15:0]rmem[0:7];
+reg [15:0]areg;
+reg [15:0]breg;
+
+always_ff @(posedge clk) begin
+	if (wreg)
+		rmem[wsel] <= wdata;
+	areg <= rmem[asel];
+	breg <= rmem[bsel];
+end
+
+assign adata = areg;
+assign bdata = breg;
+
+endmodule
+
+
+module alu16(
+	input [2:0]op,
+	input [15:0]xdata,
+	input [15:0]ydata,
+	output [15:0]rdata
+	);
+
+reg [15:0]r;
+
+always_comb begin
+	case (op)
+	3'b000: r = xdata + ydata;
+	3'b001: r = xdata - ydata;
+	3'b010: r = xdata & ydata;
+	3'b011: r = xdata | ydata;
+	3'b100: r = xdata ^ ydata;
+	3'b101: r = { {15 {1'b0}}, xdata < ydata };
+	3'b110: r = { {15 {1'b0}}, xdata >= ydata };
+	3'b111: r = xdata * ydata;
+	endcase
+end
+
+assign rdata = r;
+
+endmodule
+
diff --git a/ice40/regressions/issue0148/hdl/ice40.pcf b/ice40/regressions/issue0148/hdl/ice40.pcf
new file mode 100644
index 0000000..310e6f7
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/ice40.pcf
@@ -0,0 +1,18 @@
+set_io clk12m C2 -io_std SB_LVCMOS -pullup no
+
+set_io vga_b[0] D6 -io_std SB_LVCMOS -pullup no
+set_io vga_b[1] D5 -io_std SB_LVCMOS -pullup no
+set_io vga_g[0] E3 -io_std SB_LVCMOS -pullup no
+set_io vga_g[1] F3 -io_std SB_LVCMOS -pullup no
+set_io vga_hsync E5 -io_std SB_LVCMOS -pullup no
+set_io vga_r[0] F6 -io_std SB_LVCMOS -pullup no
+set_io vga_r[1] F5 -io_std SB_LVCMOS -pullup no
+set_io vga_vsync E6 -io_std SB_LVCMOS -pullup no
+
+set_io spi_miso F2 -io_std SB_LVCMOS -pullup no
+set_io spi_mosi D1 -io_std SB_LVCMOS -pullup no
+set_io spi_clk E1 -io_std SB_LVCMOS -pullup no
+set_io spi_cs F1 -io_std SB_LVCMOS -pullup no
+
+set_io out1 B1 -io_std SB_LVCMOS -pullup no
+set_io out2 B2 -io_std SB_LVCMOS -pullup no
diff --git a/ice40/regressions/issue0148/hdl/ice40.sdc b/ice40/regressions/issue0148/hdl/ice40.sdc
new file mode 100644
index 0000000..95762e5
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/ice40.sdc
@@ -0,0 +1,5 @@
+
+create_clock -period 83.333 -name {clk12m_in} [get_ports {clk12m_in}]
+
+create_clock -period 166.666 -name {spi_clk} [get_ports {spi_clk}]
+
diff --git a/ice40/regressions/issue0148/hdl/ice40.v b/ice40/regressions/issue0148/hdl/ice40.v
new file mode 100644
index 0000000..f2499a5
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/ice40.v
@@ -0,0 +1,222 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+`define WITH_CPU
+
+module top(
+	input clk12m_in,
+	output [1:0]vga_r,
+	output [1:0]vga_g,
+	output [1:0]vga_b,
+	output vga_hsync,
+	output vga_vsync,
+	input spi_mosi,
+	output spi_miso,
+	input spi_clk,
+	input spi_cs,
+	output out1,
+	output out2
+	);
+
+wire clk12m;
+wire clk25m;
+
+assign out1 = clk12m;
+assign out2 = clk25m;
+
+pll_12_25 pll0(
+	.clk12m_in(clk12m_in),
+	.clk12m_out(clk12m),
+	.clk25m_out(clk25m),
+	.lock(),
+	.reset(1'b1)
+	);
+
+wire sys_clk = clk12m;
+
+reg cpu_reset = 1'b0;
+
+// cpu memory interface
+wire [15:0]ins_rd_addr;
+wire [15:0]ins_rd_data;
+wire ins_rd_req;
+
+wire [15:0]dat_rw_addr;
+wire [15:0]dat_rd_data;
+wire dat_rd_req;
+wire [15:0]dat_wr_data;
+wire dat_wr_req;
+
+`ifndef WITH_CPU
+assign ins_rd_req = 1'b0;
+assign dat_rd_req = 1'b0;
+assign dat_wr_req = 1'b0;
+assign ins_rd_addr = 16'd0;
+assign dat_rw_addr = 16'd0;
+`else
+// fake arbitration that never denies a request
+reg ins_rd_rdy = 1'b0;
+reg dat_rd_rdy = 1'b0;
+reg dat_wr_rdy = 1'b0;
+
+always_ff @(posedge sys_clk) begin
+	if (cpu_reset) begin
+		ins_rd_rdy <= 1'b0;
+		dat_rd_rdy <= 1'b0;
+		dat_wr_rdy <= 1'b0;
+	end else begin
+		ins_rd_rdy <= ins_rd_req;
+		dat_rd_rdy <= dat_rd_req;
+		dat_wr_rdy <= dat_wr_req;
+	end
+end
+
+// until arbitration works
+assign dat_rd_data = 16'hEEEE;
+
+cpu16 cpu(
+	.clk(sys_clk),
+	.ins_rd_addr(ins_rd_addr),
+	.ins_rd_data(ins_rd_data),
+	.ins_rd_req(ins_rd_req),
+	.ins_rd_rdy(ins_rd_rdy),
+
+	.dat_rw_addr(dat_rw_addr),
+	.dat_wr_data(dat_wr_data),
+	.dat_rd_data(dat_rd_data),
+	.dat_rd_req(dat_rd_req),
+	.dat_rd_rdy(dat_rd_rdy),
+	.dat_wr_req(dat_wr_req),
+	.dat_wr_rdy(dat_wr_rdy),
+
+	.reset(cpu_reset)
+	) /* synthesis syn_keep=1 */;
+`endif
+
+wire [15:0]dbg_waddr;
+wire [15:0]dbg_wdata;
+wire dbg_we;
+
+spi_debug_ifc sdi(
+	.spi_clk(spi_clk),
+	.spi_cs_i(spi_cs),
+	.spi_data_i(spi_mosi),
+	.spi_data_o(spi_miso),
+	.sys_clk(sys_clk),
+	.sys_wr_o(dbg_we),
+	.sys_waddr_o(dbg_waddr),
+	.sys_wdata_o(dbg_wdata)
+	);
+
+// debug interface has priority over cpu writes
+wire we = dbg_we | dat_wr_req;
+wire [15:0]waddr = dbg_we ? dbg_waddr : dat_rw_addr;
+wire [15:0]wdata = dbg_we ? dbg_wdata : dat_wr_data;
+
+wire cs_sram = (waddr[15:12] == 4'h0);
+wire cs_vram = (waddr[15:12] == 4'h8);
+wire cs_ctrl = (waddr[15:12] == 4'hF);
+
+always @(posedge sys_clk) begin
+	if (cs_ctrl & we) begin
+		cpu_reset <= wdata[0];
+	end
+end
+
+//assign out1 = cpu_reset;
+//assign out2 = cpu_raddr[0];
+//assign out1 = dat_wr_req;
+//assign out2 = dbg_we;
+
+wire cs0r = ~ins_rd_addr[8];
+wire cs1r = ins_rd_addr[8];
+wire cs0w = ~waddr[8];
+wire cs1w = waddr[8];
+
+wire [15:0]rdata0;
+wire [15:0]rdata1;
+
+assign ins_rd_data = cs0r ? rdata0 : rdata1;
+
+sram ram0(
+	.clk(sys_clk),
+	.raddr(ins_rd_addr),
+	.rdata(rdata0),
+	.re(ins_rd_req & cs0r & cs_sram),
+	.waddr(waddr),
+	.wdata(wdata),
+	.we(we & cs0w & cs_sram)
+	);
+
+sram ram1(
+	.clk(sys_clk),
+	.raddr(ins_rd_addr),
+	.rdata(rdata1),
+	.re(ins_rd_req & cs1r & cs_sram),
+	.waddr(waddr),
+	.wdata(wdata),
+	.we(we & cs1w & cs_sram)
+	);
+
+wire [1:0]vr, vg, vb;
+
+vga40x30x2 vga(
+	.clk25m(clk25m),
+	.red(vr),
+	.grn(vg),
+	.blu(vb),
+	.hs(vga_hsync),
+	.vs(vga_vsync),
+	.fr(),
+	.vram_waddr(waddr[10:0]),
+	.vram_wdata(wdata[7:0]),
+	.vram_we(we & cs_vram),
+	.vram_clk(sys_clk)
+	);
+
+// hack: flip display from blue to red when CPU is held in reset
+assign vga_r = cpu_reset ? vb : vr;
+assign vga_g = vg;
+assign vga_b = cpu_reset ? vr : vb;
+
+endmodule
+
+module sram(
+	input clk,
+	input [15:0]raddr,
+	output [15:0]rdata,
+	input re,
+	input [15:0]waddr,
+	input [15:0]wdata,
+	input we
+	);
+
+`ifndef uselatticeprim
+reg [15:0]mem[255:0];
+reg [15:0]ra;
+always @(posedge clk) begin
+	if (we)
+		mem[waddr[7:0]] <= wdata;
+	if (re)
+		ra <= raddr;
+end
+assign rdata = mem[ra[7:0]];
+`else
+SB_RAM256x16 sram_inst(
+	.RDATA(rdata),
+	.RADDR(raddr[7:0]),
+	.RCLK(clk),
+	.RCLKE(1'b1),
+	.RE(re),
+	.WADDR(waddr[7:0]),
+	.WDATA(wdata),
+	.WCLK(clk),
+	.WCLKE(1'b1),
+	.WE(we),
+	.MASK()
+	);
+`endif
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/lattice/pll_12_25.v b/ice40/regressions/issue0148/hdl/lattice/pll_12_25.v
new file mode 100644
index 0000000..6f8104d
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/lattice/pll_12_25.v
@@ -0,0 +1,42 @@
+module pll_12_25(
+	input clk12m_in,
+	output clk12m_out,
+	output clk25m_out,
+	input reset,
+	output lock
+	);
+
+`ifndef verilator
+
+// generated by icecube2 wizard
+SB_PLL40_2_PAD pll_inst(.PACKAGEPIN(clk12m_in),
+                        .PLLOUTCOREA(),
+                        .PLLOUTCOREB(),
+                        .PLLOUTGLOBALA(clk12m_out),
+                        .PLLOUTGLOBALB(clk25m_out),
+                        .EXTFEEDBACK(),
+                        .DYNAMICDELAY(),
+                        .RESETB(reset),
+                        .BYPASS(1'b0),
+                        .LATCHINPUTVALUE(),
+                        .LOCK(lock),
+                        .SDI(),
+                        .SDO(),
+                        .SCLK());
+
+//\\ Fin=12, Fout=25;
+defparam pll_inst.DIVR = 4'b0000;
+defparam pll_inst.DIVF = 7'b1000010;
+defparam pll_inst.DIVQ = 3'b101;
+defparam pll_inst.FILTER_RANGE = 3'b001;
+defparam pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam pll_inst.PLLOUT_SELECT_PORTB = "GENCLK";
+defparam pll_inst.ENABLE_ICEGATE_PORTA = 1'b0;
+defparam pll_inst.ENABLE_ICEGATE_PORTB = 1'b0;
+
+`endif
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/nexys4.sv b/ice40/regressions/issue0148/hdl/nexys4.sv
new file mode 100644
index 0000000..5136de2
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/nexys4.sv
@@ -0,0 +1,66 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+module top(
+	input clk,
+	output reg[15:0]led
+	);
+
+wire [15:0]wdata;
+wire [15:0]waddr;
+wire [15:0]raddr;
+wire [15:0]rdata;
+wire wr;
+wire rd;
+
+assign led = raddr;
+
+sram ram0(
+        .clk(clk),
+        .waddr(waddr),
+        .wdata(wdata),
+        .we(wr),
+        .raddr(raddr),
+        .rdata(rdata),
+        .re(rd)
+	);
+
+cpu 
+`ifdef BIGCPU
+        #(
+        .RWIDTH(32),
+        .SWIDTH(5)
+        )
+`endif
+        cpu0(
+        .clk(clk),
+        .mem_raddr_o(raddr),
+        .mem_rdata_i(rdata),
+        .mem_waddr_o(waddr),
+        .mem_wdata_o(wdata),
+        .mem_wr_o(wr),
+        .mem_rd_o(rd)
+        );
+
+endmodule
+
+module sram(
+	input clk,
+	input [15:0]waddr,
+	input [15:0]wdata,
+	input [15:0]raddr,
+	output reg [15:0]rdata,
+	input we,
+	input re
+	);
+
+reg [15:0]mem[0:4095];
+
+always @(posedge clk) begin
+	if (we)
+		mem[waddr[11:0]] <= wdata;
+	if (re)
+		rdata <= mem[raddr[11:0]];
+end
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/nexys4.xdc b/ice40/regressions/issue0148/hdl/nexys4.xdc
new file mode 100644
index 0000000..381b838
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/nexys4.xdc
@@ -0,0 +1,50 @@
+
+##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
+set_property PACKAGE_PIN E3 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+
+# 100MHz
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+
+# 250MHz
+#create_clock -add -name sys_clk_pin -period 4.00 -waveform {0 2} [get_ports clk]
+
+# 200MHz
+#create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk]
+
+# 150MHz
+#create_clock -add -name sys_clk_pin -period 6.6666 -waveform {0 3.3333} [get_ports clk]
+
+set_property PACKAGE_PIN T8 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN V9 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN R8 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN T6 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+set_property PACKAGE_PIN T5 [get_ports {led[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+set_property PACKAGE_PIN T4 [get_ports {led[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+set_property PACKAGE_PIN U7 [get_ports {led[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+set_property PACKAGE_PIN U6 [get_ports {led[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+set_property PACKAGE_PIN V4 [get_ports {led[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+set_property PACKAGE_PIN U3 [get_ports {led[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+set_property PACKAGE_PIN V1 [get_ports {led[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+set_property PACKAGE_PIN R1 [get_ports {led[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+set_property PACKAGE_PIN P5 [get_ports {led[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+set_property PACKAGE_PIN U1 [get_ports {led[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+set_property PACKAGE_PIN R2 [get_ports {led[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+set_property PACKAGE_PIN P2 [get_ports {led[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+
diff --git a/ice40/regressions/issue0148/hdl/simram.sv b/ice40/regressions/issue0148/hdl/simram.sv
new file mode 100644
index 0000000..fc87f07
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/simram.sv
@@ -0,0 +1,40 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+import "DPI-C" function void dpi_mem_write(int addr, int data);
+import "DPI-C" function void dpi_mem_read(int addr, output int data);
+
+module simram(
+	input clk,
+	input [15:0]waddr,
+	input [15:0]wdata,
+	input we,
+	input [15:0]raddr,
+	output reg [15:0]rdata,
+	input re
+	);
+
+	wire [31:0]rawdata;
+	wire [31:0]junk;
+
+	// hack: this should be posedge but if we do that
+	// then the dpi_mem_write() happens too early
+	always @(negedge clk) begin
+		if (we) begin
+			$display(":WRI %08x %08x", waddr, wdata);
+			dpi_mem_write({16'd0, waddr}, {16'd0, wdata});
+		end
+	end
+	always @(posedge clk) begin
+		if (re) begin
+			dpi_mem_read({16'd0, raddr}, rawdata);
+			rdata <= rawdata[15:0];
+		end else begin
+			//junk = $random();
+			//rdata <= junk[15:0];
+			rdata <= 16'hEEEE;
+		end
+	end
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/spi_debug_ifc.v b/ice40/regressions/issue0148/hdl/spi_debug_ifc.v
new file mode 100644
index 0000000..6505c1b
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/spi_debug_ifc.v
@@ -0,0 +1,157 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+module spi_debug_ifc(
+	input spi_clk,
+	input spi_cs_i,
+	input spi_data_i,
+	output spi_data_o,
+	input sys_clk,
+	output sys_wr_o,
+	output [15:0]sys_waddr_o,
+	output [15:0]sys_wdata_o
+	);
+
+reg [15:0]spi_shift = 16'd0;
+reg [16:0]spi_data = 17'd0;
+reg [3:0]spi_count = 4'd0;
+reg spi_signal = 1'd0;
+reg spi_flag = 1'd0;
+
+assign spi_data_o = 1'b0;
+
+wire [15:0]spi_next = { spi_data_i, spi_shift[15:1] };
+
+reg [15:0]spi_shift_next;
+reg [16:0]spi_data_next;
+reg [3:0]spi_count_next;
+reg spi_signal_next;
+reg spi_flag_next;
+
+always @(*) begin
+	spi_shift_next = spi_shift;
+	spi_data_next = spi_data;
+	spi_count_next = spi_count;
+	spi_signal_next = spi_signal;
+	spi_flag_next = spi_flag;
+
+	if (spi_cs_i) begin
+		spi_count_next = 4'd0;
+		spi_flag_next = 1'b1;
+	end else begin
+		spi_shift_next = spi_next;
+		spi_count_next = spi_count + 4'd1;
+		if (spi_count == 4'd15) begin
+			spi_data_next = { spi_flag, spi_next };
+			spi_signal_next = ~spi_signal;
+			spi_flag_next = 1'b0;
+		end
+	end
+end
+
+always @(posedge spi_clk) begin
+	spi_shift <= spi_shift_next;
+	spi_data <= spi_data_next;
+	spi_count <= spi_count_next;
+	spi_signal <= spi_signal_next;
+	spi_flag <= spi_flag_next;
+end
+
+wire sys_signal;
+
+sync_oneway sync_spi_sys(
+	.txclk(spi_clk),
+	.txdat(spi_signal),
+	.rxclk(sys_clk),
+	.rxdat(sys_signal)
+	);
+
+reg sys_signal_ack = 1'b0;
+reg enabled = 1'b0;
+reg [15:0]addr;
+reg [15:0]data;
+reg wr = 1'b0;
+
+reg [15:0]addr_next;
+reg [15:0]data_next;
+reg enabled_next;
+reg sys_signal_ack_next;
+reg wr_next;
+
+reg [15:0]delay = 16'd0;
+reg [15:0]delay_next;
+
+always @(*) begin
+	delay_next = delay;
+	addr_next = addr;
+	data_next = data;
+	sys_signal_ack_next = sys_signal_ack;
+	wr_next = wr;
+
+	// ensure we're up and running before accepting writes
+	// there's got to be a nicer way to do this
+	if (delay != 16'hFFFF) begin
+		delay_next = delay + 1'd1;
+		enabled_next = 1'b0;
+	end else begin
+		enabled_next = 1'b1;
+	end
+
+	if (sys_signal ^ sys_signal_ack) begin
+		sys_signal_ack_next = ~sys_signal_ack;
+		if (spi_data[16]) begin
+			addr_next = spi_data[15:0];
+		end else begin
+			data_next = spi_data[15:0];
+			wr_next = 1'b1;
+		end
+	end else begin
+		if (wr) begin
+			wr_next = 1'b0;
+			addr_next = addr + 16'd1;
+		end
+	end
+end
+
+always @(posedge sys_clk) begin
+	delay <= delay_next;
+	addr <= addr_next;
+	data <= data_next;
+	enabled <= enabled_next;
+	sys_signal_ack <= sys_signal_ack_next;
+	wr <= wr_next;
+end
+
+assign sys_wr_o = wr & enabled;
+assign sys_waddr_o = addr;
+assign sys_wdata_o = data;
+
+endmodule
+
+
+
+module sync_oneway(
+	input txclk,
+	input txdat,
+	input rxclk,
+	output rxdat
+	);
+
+reg a = 0;
+
+// these should be adjacent
+reg b = 0, c = 0;
+
+always @(posedge txclk)
+	a <= txdat;
+
+always @(posedge rxclk) begin
+	b <= a;
+	c <= b;
+end
+
+assign rxdat = c;
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/testbench.sv b/ice40/regressions/issue0148/hdl/testbench.sv
new file mode 100644
index 0000000..c41d220
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/testbench.sv
@@ -0,0 +1,93 @@
+// Copyright 2018, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+module testbench(
+	input clk
+	);
+
+reg [15:0]count = 16'd0;
+reg reset = 1'b0;
+
+reg burp = 1'b0;
+
+always @(posedge clk) begin
+	count <= count + 16'd1;
+	burp <= (count >= 16'd0010) && (count <= 16'd0012) ? 1'b1 : 1'b0;
+	if (count == 16'd0005) reset <= 1'b0;
+	if (count == 16'd1000) $finish;
+	if (cpu.ir == 16'hFFFF) begin
+		for ( integer i = 0; i < 8; i++ ) begin
+			$display(":REG R%0d %8X", i, cpu.regs.rmem[i]);
+		end
+		$display(":END");
+		$finish;
+	end
+end
+
+wire [15:0]ins_rd_addr;
+wire [15:0]ins_rd_data;
+wire ins_rd_req;
+
+wire [15:0]dat_rw_addr;
+wire [15:0]dat_rd_data;
+wire dat_rd_req;
+wire [15:0]dat_wr_data;
+wire dat_wr_req;
+
+reg ins_rd_rdy = 1'b0;
+reg dat_rd_rdy = 1'b0;
+reg dat_wr_rdy = 1'b0;
+
+always_ff @(posedge clk) begin
+	if (reset) begin
+		ins_rd_rdy <= 1'b0;
+		dat_rd_rdy <= 1'b0;
+		dat_wr_rdy <= 1'b0;
+	end else begin
+		ins_rd_rdy <= ins_rd_req;
+		dat_rd_rdy <= dat_rd_req;
+		dat_wr_rdy <= dat_wr_req;
+	end
+end
+
+simram ins_ram(
+	.clk(clk),
+	.waddr(16'd0),
+	.wdata(16'd0),
+	.we(1'd0),
+	.raddr(ins_rd_addr),
+	.rdata(ins_rd_data),
+	.re(1'd1)
+	);
+
+simram dat_ram(
+	.clk(clk),
+	.waddr(dat_rw_addr),
+	.wdata(dat_wr_data),
+	.we(dat_wr_req),
+	.raddr(dat_rw_addr),
+	.rdata(dat_rd_data),
+	.re(dat_rd_req)
+	);
+
+cpu16 cpu(
+	.clk(clk),
+	.ins_rd_addr(ins_rd_addr),
+	.ins_rd_data(burp ? 16'hEEEE : ins_rd_data),
+	.ins_rd_req(ins_rd_req),
+	.ins_rd_rdy(ins_rd_rdy & ~burp),
+
+	.dat_rw_addr(dat_rw_addr),
+	.dat_wr_data(dat_wr_data),
+	.dat_rd_data(dat_rd_data),
+	.dat_rd_req(dat_rd_req),
+	.dat_rd_rdy(dat_rd_rdy),
+	.dat_wr_req(dat_wr_req),
+	.dat_wr_rdy(dat_wr_rdy),
+
+	.reset(reset)
+	);
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/testvga.sv b/ice40/regressions/issue0148/hdl/testvga.sv
new file mode 100644
index 0000000..2c62040
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/testvga.sv
@@ -0,0 +1,40 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+`define HEX_PATHS
+
+module testbench(
+        input clk,
+	output [3:0]vga_red,
+	output [3:0]vga_grn,
+	output [3:0]vga_blu,
+	output vga_hsync,
+	output vga_vsync,
+	output vga_frame
+        );
+
+wire [1:0]red;
+wire [1:0]grn;
+wire [1:0]blu;
+
+vga40x30x2 vga(
+	.clk25m(clk),
+	.red(red),
+	.grn(grn),
+	.blu(blu),
+	.hs(vga_hsync),
+	.vs(vga_vsync),
+	.fr(vga_frame),
+	.vram_waddr(11'b0),
+	.vram_wdata(8'b0),
+	.vram_we(1'b0),
+	.vram_clk(clk)
+	);
+
+assign vga_red = { red, red[0], red[0] };
+assign vga_grn = { grn, grn[0], grn[0] };
+assign vga_blu = { blu, blu[0], blu[0] };
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/uart.v b/ice40/regressions/issue0148/hdl/uart.v
new file mode 100644
index 0000000..daaa865
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/uart.v
@@ -0,0 +1,76 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+// more like a UAT at the moment...
+
+`timescale 1ns/1ns
+
+module uart(
+	input clk,
+	input [7:0]wdata,
+	output [7:0]rdata,
+	output busy,
+	input we,
+	output tx
+	);
+
+parameter DIVISOR = 416;
+
+reg out = 1'b1;
+reg busy = 0'b1;
+reg [7:0] data = 8'hFF;
+reg [3:0] state = 4'b0010;
+wire next_bit;
+
+uart_bit_counter counter(
+	.clk(clk),
+	.max(DIVISOR),
+	.overflow(next_bit)
+	);
+
+assign tx = out;
+assign rdata = { 7'b0, busy };
+
+always @(posedge clk) begin
+	if (!busy) begin
+		if (we) begin
+			data <= wdata;
+			busy <= 1'b1;
+		end
+	end else if (next_bit) begin
+		case (state)
+		4'b0000: begin state <= busy ? 4'b0001 : 4'b0000; out <= 1'b1; end
+		4'b0001: begin state <= 4'b0010; out <= 1'b0; end
+		4'b0010: begin state <= 4'b0011; out <= data[0]; end
+		4'b0011: begin state <= 4'b0100; out <= data[1]; end
+		4'b0100: begin state <= 4'b0101; out <= data[2]; end
+		4'b0101: begin state <= 4'b0110; out <= data[3]; end
+		4'b0110: begin state <= 4'b0111; out <= data[4]; end
+		4'b0111: begin state <= 4'b1000; out <= data[5]; end
+		4'b1000: begin state <= 4'b1001; out <= data[6]; end
+		4'b1001: begin state <= 4'b1010; out <= data[7]; end
+		4'b1010: begin state <= 4'b1011; out <= 1'b1; end
+		4'b1011: begin state <= 4'b0000; out <= 1'b1; busy <= 1'b0; end
+		endcase
+	end
+end
+
+endmodule
+
+module uart_bit_counter(
+	input clk,
+	input [15:0] max,
+	output overflow
+	);
+
+reg [15:0] count = 16'b0;
+
+assign overflow = (count == max);
+
+always @(posedge clk) begin
+	count <= overflow ? 16'b0 : (count + 16'b1);
+end
+
+endmodule
+
+
diff --git a/ice40/regressions/issue0148/hdl/vga/chardata.v b/ice40/regressions/issue0148/hdl/vga/chardata.v
new file mode 100644
index 0000000..e348e50
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/vga/chardata.v
@@ -0,0 +1,105 @@
+// Copyright 2018, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+//
+// Character Display Engine
+//
+// newline strobes on the first pixel of a new line
+// advance strobes on each visible pixel of a new line
+// line provides the visible line count 0..239
+//
+// vram_addr/vram_data: connect to sync sram
+
+`timescale 1ns/1ns
+
+module pixeldata(
+	input clk,
+	input newline,
+	input advance,
+	input [7:0] line,
+	output [11:0] pixel,
+	input [7:0] vram_data,
+	output [10:0] vram_addr
+	);
+
+reg [7:0] pattern_rom [0:1023];
+
+`ifdef HEX_PATHS
+initial $readmemh("hdl/vga/prom.txt", pattern_rom);
+`else
+initial $readmemh("prom.txt", pattern_rom);
+`endif
+
+reg next_load;
+reg [5:0] next_xpos;
+reg [3:0] next_ppos;
+reg [15:0] next_pattern;
+
+reg load = 1'b0;
+reg [5:0] xpos = 6'b0;
+reg [3:0] ppos = 4'b0;
+reg [15:0] pattern = 16'b0;
+
+// generate vram address by using the high bits of the display
+// line and the local xpos character counter
+assign vram_addr = { line[7:3], next_xpos };
+
+// generate pattern rom address by using the character id
+// fetched from vram as the high bits and the low bits of
+// the display line to further index into the correct pattern
+wire [9:0] pattern_addr = { vram_data[6:0], line[2:0] };
+
+`ifdef ASYNC_ROM
+wire [7:0] cdata = pattern_rom[pattern_addr];
+`else
+reg [7:0] cdata;
+always_ff @(posedge clk)
+	cdata <= pattern_rom[pattern_addr];
+`endif
+
+
+// the high bit of the pattern shift register is used to
+// select the FG or BG color and feed out to the vga core
+assign pixel = pattern[15] ? 12'hFFF : 12'h00F;
+
+always_comb begin
+	next_xpos = xpos;
+	next_ppos = ppos;
+	next_pattern = pattern;
+	next_load = 1'b0;
+
+	if (newline) begin
+		next_load = 1'b1;
+		next_xpos = 6'b0;
+		next_ppos = 4'b0;
+	end else if (advance) begin
+		next_ppos = ppos + 4'h1;
+		if (ppos == 4'hF) begin
+			next_load = 1'b1;
+			next_xpos = xpos + 6'b1;
+		end
+	end
+
+	// pattern shift register
+	if (load) begin
+		// 8bit wide character pattern line is expanded 
+		// into the 16bit pattern shift register
+		next_pattern = {
+			cdata[7], cdata[7], cdata[6], cdata[6],
+			cdata[5], cdata[5], cdata[4], cdata[4],
+			cdata[3], cdata[3], cdata[2], cdata[2],
+			cdata[1], cdata[1], cdata[0], cdata[0]
+			};
+	end else if (advance) begin
+		next_pattern = { pattern[14:0], 1'b0 };
+	end
+
+end
+
+always_ff @(posedge clk) begin
+	load <= next_load;
+	xpos <= next_xpos;
+	ppos <= next_ppos;
+	pattern <= next_pattern;
+end
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/vga/prom.txt b/ice40/regressions/issue0148/hdl/vga/prom.txt
new file mode 100644
index 0000000..65c5735
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/vga/prom.txt
@@ -0,0 +1,1024 @@
+00
+00
+00
+00
+00
+00
+00
+00
+00
+3e
+41
+55
+41
+55
+49
+3e
+00
+3e
+7f
+6b
+7f
+6b
+77
+3e
+00
+22
+77
+7f
+7f
+3e
+1c
+08
+00
+08
+1c
+3e
+7f
+3e
+1c
+08
+00
+08
+1c
+2a
+7f
+2a
+08
+1c
+00
+08
+1c
+3e
+7f
+3e
+08
+1c
+00
+00
+1c
+3e
+3e
+3e
+1c
+00
+ff
+ff
+e3
+c1
+c1
+c1
+e3
+ff
+00
+00
+1c
+22
+22
+22
+1c
+00
+ff
+ff
+e3
+dd
+dd
+dd
+e3
+ff
+00
+0f
+03
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diff --git a/ice40/regressions/issue0148/hdl/vga/vga.v b/ice40/regressions/issue0148/hdl/vga/vga.v
new file mode 100644
index 0000000..eb37690
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/vga/vga.v
@@ -0,0 +1,101 @@
+// Copyright 2012, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns/1ns
+
+// Vert:  2xSync 30xBack 480xData 12xFront  -> 524 lines
+// Horz: 96xSync 48xBack 640xData 16xFront  -> 800 pixels
+//
+// CLK: 25MHz, px=40nS, line=32uS, frame=16.768mS
+
+module vga(
+	input clk,
+	output hs,
+	output vs,
+	output fr,
+	output [3:0] r,
+	output [3:0] g,
+	output [3:0] b,
+
+	output newline,
+	output advance,
+	output [7:0] line,
+	input [11:0] pixel
+	);
+
+reg hsync = 1'b0;
+reg vsync = 1'b0;
+reg frame = 1'b0;
+reg active = 1'b0;
+reg startline = 1'b0;
+reg [9:0] hcount = 10'b0;
+reg [9:0] vcount = 10'b0;
+
+reg next_hsync;
+reg next_vsync;
+reg next_frame;
+reg next_active;
+reg next_startline;
+reg [9:0] next_hcount;
+reg [9:0] next_vcount;
+
+wire [9:0] adjusted_vcount = next_vcount - 10'd32;
+
+assign hs = hsync;
+assign vs = vsync;
+assign fr = frame;
+assign line = adjusted_vcount[8:1];
+assign advance = active;
+assign newline = startline;
+
+assign r = active ? pixel[11:8] : 4'd0;
+assign g = active ? pixel[7:4] : 4'd0;
+assign b = active ? pixel[3:0] : 4'd0;
+
+always_comb begin
+	next_hsync = hsync;
+	next_vsync = vsync;
+	next_frame = 1'b0;
+	next_active = 1'b0;
+	next_startline = 1'b0;
+	next_hcount = 10'd0;
+	next_vcount = 10'd0;
+
+	if (hcount == 10'd799) begin
+		if (vcount == 10'd523) begin
+			next_vcount = 10'd0;
+			next_frame = 1'b1;
+			next_vsync = 1'b0;
+		end else
+			next_vcount = vcount + 10'd1;
+		next_hcount = 10'd0;
+		next_hsync = 1'b0;
+		next_startline = 1'b1;
+	end else begin
+		next_vcount = vcount;
+		next_hcount = hcount + 10'd1;
+	
+		if (hcount == 10'd96)
+			next_hsync = 1'b1;
+
+		if (vcount == 10'd2)
+			next_vsync = 1'b1;
+
+		if ((vcount > 30) && (vcount < 511))
+			if ((hcount > 142) && (hcount < 783))
+				next_active = 1'b1;
+	end
+
+end
+
+always_ff @(posedge clk) begin
+	hsync <= next_hsync;
+	vsync <= next_vsync;
+	frame <= next_frame;
+	active <= next_active;
+	startline <= next_startline;
+	hcount <= next_hcount;
+	vcount <= next_vcount;
+end
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/vga/vga40x30x2.v b/ice40/regressions/issue0148/hdl/vga/vga40x30x2.v
new file mode 100644
index 0000000..1d2fd09
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/vga/vga40x30x2.v
@@ -0,0 +1,69 @@
+// Copyright 2012, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+module vga40x30x2(
+	input clk25m,
+	output [1:0]red,
+	output [1:0]grn,
+	output [1:0]blu,
+	output hs,
+	output vs,
+	output fr,
+	input vram_clk,
+	input [10:0]vram_waddr,
+	input [7:0]vram_wdata,
+	input vram_we
+	);
+
+wire [3:0]r;
+wire [3:0]g;
+wire [3:0]b;
+
+wire newline;
+wire advance;
+wire [7:0]line;
+wire[11:0]pixel;
+
+vga vga0(
+	.clk(clk25m),
+	.hs(hs),
+	.vs(vs),
+	.fr(fr),
+	.r(r),
+	.g(g),
+	.b(b),
+	.newline(newline),
+	.advance(advance),
+	.line(line),
+	.pixel(pixel)
+	);
+
+assign red = r[3:2];
+assign grn = g[3:2];
+assign blu = b[3:2];
+
+wire [10:0]vram_raddr;
+wire [7:0]vram_rdata;
+
+pixeldata pixeldata0(
+	.clk(clk25m),
+	.newline(newline),
+	.advance(advance),
+	.line(line),
+	.pixel(pixel),
+	.vram_data(vram_rdata),
+	.vram_addr(vram_raddr)
+	);
+
+videoram #(8,11) vram(
+	.rclk(clk25m),
+	.re(1'b1),
+	.rdata(vram_rdata),
+	.raddr(vram_raddr),
+	.wclk(vram_clk),
+	.we(vram_we),
+	.wdata(vram_wdata[7:0]),
+	.waddr(vram_waddr[10:0])
+	);
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/vga/videoram.v b/ice40/regressions/issue0148/hdl/vga/videoram.v
new file mode 100644
index 0000000..46ccaac
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/vga/videoram.v
@@ -0,0 +1,38 @@
+// Copyright 2012, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+//
+// sync sram with independent read/write addressing
+
+`timescale 1ns/1ns
+
+module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
+	input wclk, input we,
+	input [AWIDTH-1:0] waddr,
+	input [DWIDTH-1:0] wdata,
+	input rclk, input re,
+	input [AWIDTH-1:0] raddr,
+	output [DWIDTH-1:0] rdata
+	);
+
+reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+reg [DWIDTH-1:0] data;
+
+assign rdata = data;
+
+`ifdef HEX_PATHS
+initial $readmemh("hdl/vga/vram.txt", mem);
+`else
+initial $readmemh("vram.txt", mem);
+`endif
+
+always @(posedge wclk) begin
+	if (we)
+		mem[waddr] <= wdata;
+end
+
+always @(posedge rclk) begin
+	if (re)
+		data <= mem[raddr];
+end
+
+endmodule
diff --git a/ice40/regressions/issue0148/hdl/vga/vram.txt b/ice40/regressions/issue0148/hdl/vga/vram.txt
new file mode 100644
index 0000000..77b0319
--- /dev/null
+++ b/ice40/regressions/issue0148/hdl/vga/vram.txt
@@ -0,0 +1,2048 @@
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diff --git a/ice40/regressions/issue0148/ice40.json b/ice40/regressions/issue0148/ice40.json
new file mode 100644
index 0000000..9e841f5
--- /dev/null
+++ b/ice40/regressions/issue0148/ice40.json
@@ -0,0 +1,52198 @@
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+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:58|hdl/vga/videoram.v:10"
+          }
+        },
+        "vga.vram.wclk": {
+          "hide_name": 0,
+          "bits": [ 11 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:58|hdl/vga/videoram.v:9"
+          }
+        },
+        "vga.vram.wdata": {
+          "hide_name": 0,
+          "bits": [ 528, 530, 532, 534, 536, 538, 540, 542 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:58|hdl/vga/videoram.v:11"
+          }
+        },
+        "vga.vram.we": {
+          "hide_name": 0,
+          "bits": [ 1006 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:58|hdl/vga/videoram.v:9"
+          }
+        },
+        "vga.vram_clk": {
+          "hide_name": 0,
+          "bits": [ 11 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:12"
+          }
+        },
+        "vga.vram_raddr": {
+          "hide_name": 0,
+          "bits": [ 931, 934, 938, 942, 946, 950, 906, 908, 999, 1660, 1662 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:45"
+          }
+        },
+        "vga.vram_rdata": {
+          "hide_name": 0,
+          "bits": [ 1690, 1691, 1692, 1693, 1694, 1695, 1696, 1773 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:46"
+          }
+        },
+        "vga.vram_waddr": {
+          "hide_name": 0,
+          "bits": [ 192, 276, 279, 198, 362, 360, 179, 40, 504, 515, 526 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:13"
+          }
+        },
+        "vga.vram_wdata": {
+          "hide_name": 0,
+          "bits": [ 528, 530, 532, 534, 536, 538, 540, 542 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:14"
+          }
+        },
+        "vga.vram_we": {
+          "hide_name": 0,
+          "bits": [ 1006 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:15"
+          }
+        },
+        "vga.vs": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "hdl/ice40.v:165|hdl/vga/vga40x30x2.v:10"
+          }
+        },
+        "vga_b": {
+          "hide_name": 0,
+          "bits": [ 5, 5 ],
+          "attributes": {
+            "src": "hdl/ice40.v:12"
+          }
+        },
+        "vga_g": {
+          "hide_name": 0,
+          "bits": [ 4, 4 ],
+          "attributes": {
+            "src": "hdl/ice40.v:11"
+          }
+        },
+        "vga_hsync": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "hdl/ice40.v:13"
+          }
+        },
+        "vga_r": {
+          "hide_name": 0,
+          "bits": [ 3, 3 ],
+          "attributes": {
+            "src": "hdl/ice40.v:10"
+          }
+        },
+        "vga_vsync": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "hdl/ice40.v:14"
+          }
+        },
+        "vr": {
+          "hide_name": 0,
+          "bits": [ 4, 4 ],
+          "attributes": {
+            "src": "hdl/ice40.v:163"
+          }
+        },
+        "waddr": {
+          "hide_name": 0,
+          "bits": [ 192, 276, 279, 198, 362, 360, 179, 40, 504, 515, 526, "x", 1886, 1887, 1888, 1889 ],
+          "attributes": {
+            "src": "hdl/ice40.v:115"
+          }
+        },
+        "wdata": {
+          "hide_name": 0,
+          "bits": [ 528, 530, 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, 556, 558 ],
+          "attributes": {
+            "src": "hdl/ice40.v:116"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0148/ice40.npnr b/ice40/regressions/issue0148/ice40.npnr
new file mode 100644
index 0000000..7f0606f
--- /dev/null
+++ b/ice40/regressions/issue0148/ice40.npnr
@@ -0,0 +1 @@
+--package sg48 --up5k
diff --git a/ice40/regressions/issue0148/ice40.pcf b/ice40/regressions/issue0148/ice40.pcf
new file mode 100644
index 0000000..db51c60
--- /dev/null
+++ b/ice40/regressions/issue0148/ice40.pcf
@@ -0,0 +1,18 @@
+set_io clk12m_in 35
+
+set_io vga_r[0] 23
+set_io vga_g[0] 25
+set_io vga_r[1] 26
+set_io vga_g[1] 27
+set_io vga_b[1] 32
+set_io vga_b[0] 31
+set_io vga_hsync 34
+set_io vga_vsync 43
+
+set_io spi_miso 14
+set_io spi_mosi 17
+set_io spi_clk 15
+set_io spi_cs 16
+
+set_io out1 3
+set_io out2 4
diff --git a/ice40/regressions/issue0148/ice40.ys b/ice40/regressions/issue0148/ice40.ys
new file mode 100644
index 0000000..9e9681c
--- /dev/null
+++ b/ice40/regressions/issue0148/ice40.ys
@@ -0,0 +1,10 @@
+verilog_defines -DHEX_PATHS -DYOSYS
+read_verilog -sv hdl/ice40.v
+read_verilog -sv hdl/spi_debug_ifc.v
+read_verilog -sv hdl/lattice/pll_12_25.v
+read_verilog -sv hdl/cpu16.sv
+read_verilog -sv hdl/vga/vga40x30x2.v
+read_verilog -sv hdl/vga/vga.v
+read_verilog -sv hdl/vga/videoram.v
+read_verilog -sv hdl/vga/chardata.v
+synth_ice40 -top top -json ice40.json